Speaker
Description
Motivated by the Upstream Pixel tracker in the LHCb Upgrade II and future electron-positron collider, COFFEE series chips are developed in a 55nm HVCMOS process. While maintaining a fine spatial resolution and reasonable power consumption, we aim to achieve a few nanosecond timing under hit density up to 100 MHz/cm$^2$. Building on the first validation chip with in-pixel amplification, a new prototype, COFFEE3, is designed and being tested. Two schemes for high density readout were included: analog pixel with improved column readout and a digital pixel with TDC. This talk will discuss the design details and shows the first results.
Summary (500 words)
Motivated by the Upstream Pixel tracker in the LHCb Upgrade II and future electron-positron collider, COFFEE series chips are developed in a 55nm HVCMOS process. While maintaining a fine spatial resolution and reasonable power consumption, we aim to achieve a few nanosecond timing under hit density up to 100 MHz/cm2. Building on the validation of sensing diode and the in-pixel amplification in COFFEE2, COFFEE3 in this work focuses on the time measurement and high density hit readout. Two distinct readout schemes and some test structures are developed.
The first scheme is similar with MightyPix and ATLASPix with only NMOS transistors to avoid crosstalk between the deep-Nwell sensing diode and Nwell-hosted PMOS transistors. The pre-amplifier and discriminator are integrated in pixel. The arrival times of the leading and trailing edges of the distinguished hits are recorded in the column level. However, MightyPix and ATLASPix accepted hit density up to 35 MHz/cm2. Owing to the small feature size of 55 nm process, we can integrate more circuits for one column. The pixels in a column are grouped into 4 channels. The 4 channels work parallel at the end of column. In addition, each channel can correctly process up to two simultaneous hits with an improving readout control. Eventually, the hit density up to 100 MHz/cm2 can be accepted.
The second scheme aims to explor the potential of the 55nm feature size with a pixel-level time measurement approach. Both NMOS and PMOS transistors are used in the pixel design, since P+ isolation between the Nwell and deep Nwell can be introduced in the future process. The in-pixel front-end analog circuits achieve a time walk of ~12 ns and jitter of ~2 ns. The time information is sampled and stored in the pixel level. The coarse time is from the timestamps, which is fanned out from peripheral circuitry. The fine time is derived from a voltage-controlled delay line (VCDL). A digital locked loop (DLL) is implemented in the peripheral circuitry, while VCDL replica is integrated into each pixel. The least significant bit (LSB) resolutions are 4.2 ns for the leading edge and 8.4 ns for the trailing edge. To reduce power consumption, the signal distribution of timestamps employs power gating, and only hit pulses (not clocks) are sent to the VCDL. The simulation results indicate that pile-up can be avoid if one pixel can be read out in three clock cycles (75 ns).
COFFEE3 was submitted in January 2025. In the submission, above two design schemes and some test structure of passive sensing diode are included. The first scheme features a 32×12 array with 40μm×100μm pixels, the second scheme is a 48×12 array with pixel dimensions of 40μm×145μm. The test setup is preparing. The first results of HVCMOS pixel sensor with 55 nm process will be presented in the coming workshop.