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Description
This paper presents the design of high-speed readout controller dedicated for pixel detectors. Communication with imaging sensors is asymmetric in its nature. Configuration, calibration and control data transfers are typically not time-critical or are composed of relatively short commands. In the other direction, it is desired to transfer image data as fast as possible. Having that in mind, the developed controller is divided into control path and readout path. Control path is responsible for loading configuration data and controlling chip operation. Readout path on the other hand is unidirectional and designed for high data throughput by utilizing multigigabit serializer.
Summary (500 words)
SPHIRD ASIC is dedicated to high count rate single photon counting operation at the European Synchrotron Radiation Facility with Extremely Brilliant Source. The prototype IC has a matrix of 64×32 pixels with 50μm pitch. Pixel front-end electronics employs novel pile-up compensation techniques [1], while pixel logic uses relocation algorithms to increase spatial resolution [2]. This paper focuses on readout controller, responsible for matrix readout and implementing a dedicated communication protocol.
Communication with imaging sensors is asymmetric in its nature. Configuration, calibration and control data has to be sent to the sensor. These transfers are typically not time-critical or are composed of relatively short commands, hence a single, source-synchronous link is sufficient. However, in the other direction, it is desired to transfer image data as fast as possible, thus a high-speed, multigigabit serializer is a preferred option.
Having that in mind, the developed controller is divided into two parts: control path and readout path. Control path is responsible for loading configuration data to the pixel matrix and controlling chip operation. This path is bidirectional - it allows also to read status registers or image data at lower speed. Readout path on the other hand is unidirectional and designed for high data throughput. It uses an on-chip 4-lane serializer together with PCS (Physical Coding Sublayer), capable of line rates of 4Gbps per lane.
The developed low-level communication protocol is designed for robustness and deterministic operation. It allows for automatic connection setup, transmission errors detection and link reinitialization after connection lost. The operation and link handling is done autonomously, which simplifies integration with detector.
The controller has been successfully launched and tested with FPGA evaluation board, achieving data rates of 10.7Gbps. At the conference we will describe the implementation details of the controller and the communication protocol, partitioning of functionality between the integrated circuit and reading system and present planned application.
- P. Grybos., "SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods," IEEE TCAS II, vol. 70, no. 9, pp. 3248-3252, 2023, doi: 10.1109/TCSII.2023.3267859.
- P. Otfinowski., "Increasing the Position Resolution in Single Photon Counting Pixel Readout IC by Real-Time Interpixel Communications," IEEE TCAS II, vol. 71 no. 8, s. 3695-3699, 2024 doi: 10.1109/TCSII.2024.3372884.