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Description
The ALICE ITS3 project will upgrade the inner silicon tracker layers with wafer-scale (27cm long) MAPS bent around the beampipe. The MAPS transfers its pixel data via 10.24-Gbps differential links driving a 30cm long FPC-cable.
The NKF7 proto-chip serialises a 16-bit static input to 10.24-Gbps output with a measured Bit Error Rate (BER)<10^-15. Irradiation with 32-MeV protons gives σSEU≈10^-12cm2 and NKF7 withstands a TID>10MRad.
Connecting NKF7 16-data inputs to an FPGA allows PRBS generation with (including FPC-cable) open eyes at 5.12-Gbps (BER<10^-15) but closed at 10.24-Gbps (BER>10^-6), possibly originating from bondwire self-induced supply noise and structural DLL bin width deviations.
Summary (500 words)
ALICE will upgrade its inner three silicon tracker layers (ITS3). Each layer comprises two wafer-scale MAPS (Monolithic Active Pixel Sensors) bent to concentric half-layers around the beam pipe (radii: 19, 25, 32 mm). Fabrication requires stitching at foundry level connecting 12 identical reticle-sized RSU (Repeated Sensor Units) to endcaps on both sides.
Power is provided from both endcaps. All data, clock and control signals go through the LEC (Left End Cap). Each RSU has 1.65 MPixels whose data are transmitted on chip through twelve 160 Mbps links to the LEC. The LEC aggregates, encodes and serialises all data to 6 or 3 (5.12 or 10.24-Gbps) data transmission links. These links are connected via a 30 cm Flexible Printed Circuit (FPC) cable to (VTRx+) optical links.
To evaluate the performance of a serializer in MAPS, a prototype chip (NKF7) was developed in 65nm Tower-Jazz technology. This chip has a 16-bit parallel bus input, a 640 MHz clock input and a 10.24-Gbps 100Ω differential data output. The ITS3NKF7 carrier, designed to set a fixed 16-bit data-pattern by switches, combined with the KC705 FPGA transceiver was used to measure the Bit Error Rate (BER) which was <10^-15.
This “fixed pattern setup” also characterised the NKF7 chip with 32 MeV protons at the NPI Rez cyclotron. The measured cross section was σ=#BitErrors/Fluence≈10^-12cm2 and no degradation was observed for an integrated dose of 10 Mrad. Under ITS3 conditions (flux 1 MHz cm-2), the single link radiation-induced BER becomes ≈10^-16.
The NKF7FMC carrier was designed to enable NKF7 for variable/PRBS-pattern generation by connecting the 16 data inputs to an FPGA via an FMC interface. As NKF7 requires each of the 16 LVCMOS data signals to arrive at a different phase within the 640MHz clock period, a FPGA with accurate low jitter IO-delay features was selected. To minimise timing degradation, the data was sent using LVDS, requiring (640 MHz) LVDS to LVCMOS buffer characterisation.
The firmware for the NKF7FMC placed on a ZCU102 FPGA board allows the generation of PRBS patterns at 10.24 Gbps, as well as 5.12 Gbps by duplicating successive bits. At 5.12 Gbps, the eyes are wide open even including the FPC cable (BER< 10^-15). At 10.24 Gbps, the eye closes (BER>10^-6 below Vsupply=1.35V) and is fully closed including the FPC cable.
The NKF7 output signal quality degrades for lower supply voltages. Simulations suggest this is caused by power supply noise induced by bond wire inductances. In addition, tests with an alternating pattern (0x5555) show for each of the 16 bit widths large structural deviations (±10ps at Vsupply=1.35V and increases for lower Vsupply) from the ideal bit width (=97.7ps), possibly related to deviations in DLL bin width.
The serializer block (GWT_PSI) designed for the next ITS3 prototype chip (MOSAIX) is a significantly improved descendant of the NKF7 prototype. Multiple integrated low-dropout linear regulators (LDOs) have been added, reducing self-induced supply noise and minimising DLL and PLL jitter by improving the VCO. The high speed line driver bandwidth is increased and optional pre-emphasis is added.
