Speaker
Description
Next‑generation pixel‑based read‑out ASICs for high‑energy physics experiments
face demanding performance and integration requirements. A flexible, pixel‑level
simulation framework is essential to design, validate, and optimize the read‑out
architecture and its building blocks. We present a SystemVerilog/UVM
verification environment developed for the IGNITE project, a 28 nm CMOS pixel
read‑out and processing ASIC designed for high‑intensity 4D‑tracking with $<10
\mu$m spatial and $< 50$ps temporal resolution in harsh radiation
environments. The verification environment comprises modular components for
configuration, parameterized random and cluster hit generation, and I/O
monitoring. Coverage analysis confirmed that all critical logic was thoroughly
exercised.
Summary (500 words)
Driven by ever‑increasing requirements of modern high‑energy physics
experiments, next‑generation pixel read‑out ASICs must achieve sub-10 $\mu$m
spatial resolution and sub‑50 ps timing resolution, all while keeping power
densities below 1 $\text{W}/\text{cm}^{2}$, and within extreme radiation environments
(fluence > $1 \times 10^{6}$ 1 MeV equivalent neutrons per $\text{cm}^2$ and total
ionizing doses up to 1 Grad). To address these demanding targets, the IGNITE
project is developing a 28 nm CMOS pixel read‑out and processing ASIC tailored
for high‑intensity 4D tracking in extreme radiation environments.
Ensuring first-silicon success demands a comprehensive verification strategy. We
have developed a fully modular SystemVerilog/UVM environment built from reusable
Universal Verification Components (UVCs) in accordance with industry best
practices. A register-abstraction layer, automatically generated from Accellera
SystemRDL, ensures robust and maintainable register configuration and access.
Programmable clock generators support multiple domains with user-defined jitter
and phase control, while a flexible hit-stimulus generator, driven in parallel
by a custom C++ program to generate stimuli and accelerate simulation runtimes,
produces randomized single-pixel and clustered patterns to emulate realistic
sensor outputs. Protocol agents drive and monitor GPIO interfaces to verify
protocol compliance and end-to-end data integrity across all operating modes.
To quantify verification progress, functional coverage models track exercised
scenarios across diverse hit patterns and register states. Coverage metrics
guide targeted test creation, ensuring gaps are methodically closed. Applied to
the IGNITE ASIC, this framework executed over $1.0 \times 10^6$ hit sequences across
every mode and achieved 98.0\% functional coverage. These results demonstrate
the environment’s capability to drive rigorous, data-driven verification of
advanced pixel readout logic and interfaces. Moreover, the modular components
and best practices detailed here promise to streamline development of future
ASIC designs.
