Speaker
Description
The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in high-energy physics. MOSAIX, a fully functional prototype and the final development step before production, measures 266 mm by 19 mm. The chip integrates 144 independently powered pixel matrices, eight 10 Gbps transmitters, and on-chip power and data distribution.
This contribution presents the development of the MOSAIX test system and verification strategy, with emphasis on validating the testing infrastructure before chip availability. The system includes an FPGA that controls MOSAIX and parses its output, and a second MOSAIX emulator FPGA.
Summary (500 words)
The MOSAIX is a wafer-scale, monolithic CMOS sensor ASIC developed for ALICE ITS3. Each of the three ITS3 layers consists of two pieces of silicon, each measuring 266 mm by 56-94 mm subdivided into 3-5 independent MOSAIX segments (depending on the layer). Each segment is powered and controlled independently. The MOSAIX allows for replacing a distributed readout and control architecture, where readout, control, and power management are handled by external components, by integrating services on the chip. Each segment comprises 144 independently powered and controlled pixel matrices, a configurable readout processor with eight lpGBT compatible 10 Gbps transmitters, and a stitched data, control and power bus connecting all pixel matrices to the readout processor and the power lines over 266 mm. This high level of integration poses new verification and qualification challenges, such as validating long-distance signal integrity across stitched interconnects, synchronizing hundreds of pixel matrices, and qualifying high-speed data transmission already at wafer level. In addition, the increased system complexity pushes the operation of the MOSAIX beyond standard ASIC procedures.
A modular and reusable test system has been developed, based on an FPGA processor card. Modularity is achieved through adapter boards allowing easy adaptation to different test setups. Reusability comes from designing the system to support both current MOSAIX prototypes and future design iterations. The FPGA firmware handles communication, data processing, and monitoring, while a dedicated software stack manages configuration, data acquisition, and control.
This infrastructure supports different test stages and test setups corresponding to the progression of the chip testing and qualification: from power-up and communication, to testing the data path, pixel matrix functionality, and the high-speed transmitters. The test system supports multiple test setups, including (1) probing the full chip on wafer, (2) individual wire-bonded segments mounted on a large carrier PCB, and (3) full-scale ITS3 layer, using the same mechanical and electrical configuration as the final ITS3. The same infrastructure supports future design iterations, ensuring consistent evaluation.
Validating the testing infrastructure before fabrication reduces risk and ensures readiness when silicon arrives. Furthermore, it may reveal MOSAIX design issues prior to tape-out.
A central feature of the verification strategy is the use of an FPGA-based MOSAIX emulation. We emulate key functional blocks of the MOSAIX and use it to develop and verify firmware and software before MOSAIX is available. The emulator FPGA connects via all relevant interfaces—direct links, the carrier board, the flexible printed circuit, or the wafer prober card—allowing full qualification of hardware, firmware, and software together. The emulator model includes actual RTL MOSAIX blocks of the control and data paths, and in some cases, lightweight models where full implementation is impractical, such as pixel matrices and analog circuitry. Emulation allows us to detect integration issues early, accelerate the development timeline, and ensure that software and firmware are mature when MOSAIX becomes available.
This contribution presents the test system and qualification approach, highlighting how early validation mitigates integration risks and accelerates the deployment of MOSAIX within the ALICE ITS3 upgrade.