Speaker
Description
The upcoming Phase-2 upgrade of the LHC presents significant challenges for CMS Back-End electronics due to dramatic increase in trigger rate, data volume, and system complexity. The system must handle L1A rates up to 750kHz with a L1A latency of 12us. The EMP Common Readout firmware addresses these needs, as a modular and flexible system designed to unify trigger event data collection across CMS Back-End Phase-2 subsystems. This contribution presents the architecture and implementation of the EMP Common Readout, along with results from high-rate tests across multiple setups as well as beam test data-taking, with billions of events recorded.
Summary (500 words)
The upcoming Phase-2 upgrade of the LHC presents significant challenges for CMS Back-End electronics due to the dramatic increase in trigger rates, data volume, and system complexity. The system must handle Level-1 Accept (L1A) trigger rates up to 750 kHz, store large volumes of data during the L1A latency period, support high-throughput detectors such as the High Granularity Endcap Calorimeter (HGCAL), and maintain synchronization across a diverse array of subdetectors and processing nodes. These constraints demand scalable, reconfigurable firmware capable of operating at high throughput with minimal latency and robust fault recovery mechanisms.
The EMP (Extensible Modular Processing) Common Readout firmware addresses these needs, as a modular and flexible system designed to unify trigger event data collection across CMS Back-End subsystems for Phase-2. Developed within the EMP framework, it enables selective, structured capture of both input and output data from trigger boards for purposes such as validation, emulation, and system debugging. The design supports both Time-Multiplexed (TM) and non-TM system architectures and accommodates the low-power Gigabit Transceiver (lpGBT) protocol and the CMS Standard Protocol (CSP).
Streams for each board in the trigger subsystems are buffered in latency buffers and routed into event FIFOs upon receiving an L1A. Two distinct readout modes are implemented: regular readout intended for the majority of L1As (~750 kHz), and “extended readout” for lower-rate prescaled triggers (~7.5 kHz), capturing extra data and/or multiple bunch crossings (BXs) around the L1A for in-depth validation. Readout packets are collected using a daisy-chain architecture and formatted for transmission to the central CMS data acquisition (DAQ) system using the SlinkRocket protocol. Each active Multi-Gigabit Transceiver (MGT) Quad in an FPGA hosts a Common Readout Quad block, which manages all four RX and TX channels. A centralized daisy-chain controller and a SLINK formatter coordinate synchronization and flow control toward the central DAQ system.
The firmware is highly configurable, with firmware generics and software control registers. These allow for selecting different TM ratios, enabling or disabling regular readout per channel, masking unused channels, configuring the size of the extended windows, and setting the number of captured words per BX. A dedicated reset mechanism allows system recovery without affecting the full EMP framework, and a packet truncation mechanism maintains synchronization even when buffers overflow.
The Common Readout firmware will also be an invaluable tool for the validation and commissioning of the various components of the Phase-2 CMS subdetectors.
The scope of this contribution is to present the challenges faced and the architectural choices made to address them. Moreover, results will be presented from extensive testing with multiple CMS Back-End boards (Serenity, Apollo) at average trigger rates of up to 1 MHz, above the CMS Level-1 nominal trigger rate of 750 kHz. In addition, results will be shown from beam tests performed in 2024 for the HGCAL, using the Common Readout to capture trigger data for several billion events. Finally, we will present the anticipated future developments aimed at integrating zero suppression and improving throughput performance.