Speaker
Description
Reliable, cost-effective and scalable interconnect technologies are crucial for hybrid pixel detectors. Within the CERN EP-R&D programme and the AIDAinnova collaboration, a portfolio of single-die post-processing and hybridization techniques has been developed, especially suitable for small-volume productions. These include conductive adhesives (ACF and ACA) combined with in-house Ni/Au plating for fine-pitch hybridization down to 25 microns, as well as low-temperature gold-stud bonding with epoxy underfill for ~mm pitches. Connectivity yields up to 97% have been achieved on devices with 55 µm pitch and bonding areas up to 2 cm2 and up to 100% for large-pitch devices.
Summary (500 words)
In the development of hybrid pixel detectors, a reliable and cost-effective interconnect technology is essential. Traditional wafer-level interconnection techniques, such as solder bumps and copper pillars, while effective, demand complex industrial process lines and entail high costs. These challenges become particularly significant for sensors and ASICs produced in small volumes or via Multi-Project Wafers (MPW), where no industrial provider currently offers standardized single-chip hybridization services. As hybrid pixel detector technology advances towards finer pitches and higher densities, there is a strong demand for innovative and scalable assembly techniques, especially during prototyping phases.
Within the CERN EP-R&D programme and in collaboration with Geneva University and the AIDAinnova consortium, a portfolio of innovative single-die hybridization processes has been developed. This includes processes relying on Anisotropic Conductive Adhesives (ACA) — both Anisotropic Conductive Films (ACF) and Pastes (ACP) — combined with in-house Electroless Nickel Immersion Gold (ENIG) plating. Adapted from techniques used in the display industry, this method enables fine-pitch interconnection between sensors and ASICs, offering a versatile and cost-effective solution for prototyping and small-scale production.
The ACA and ENIG-based hybridization approach has been extensively studied across a wide range of ASICs and sensors from different R&D projects. Examples include KEK-AC-LGAD (40 µm pad diameter, 100 µm pitch, 1.2 mm2 area), Timepix3 (12–14 µm pad diameter, 55 µm pitch, 2 cm² area), ESRF SPHIRD (15 µm pad diameter, 50 µm pitch, 5 mm² area), ALTIROC2/3/A (90 µm pad diameter, 1.3 mm pitch, 4 cm² area), and small-pitch test structures (12 µm pad diameter, 25 µm pitch, 2.6 mm² area). Connectivity yields up to 97% have been achieved on test structures produced at FBK-Trento, which replicate the pitch and pad size characteristics of Timepix3 devices. Comprehensive electrical characterization, including thermal cycling between -40°C and 120°C, has demonstrated the robustness and durability of these hybrid assemblies.
Recently, promising results have been obtained in the hybridization of small-size Trench-isolated Low-Gain-Avalanche-Detector (TiLGAD) sensors onto Timepix3 ASICs, using the ENIG and ACF processes. These hybrids have been characterized using radioactive sources, achieving a connection yield of approximately 95%. Further evaluations including test-beam measurements are currently ongoing to fully assess the particle-detection performance.
In parallel, an alternative hybridization technique has been developed, based on individually deposited gold-studs on the pads of the chips. In this method, mechanical strength between the dies is provided by an epoxy adhesive, while the gold-studs ensure electrical connectivity. This approach offers another flexible solution for hybridization at the single-die level, and is especially suited for the hybridization of irradiated sensors requiring a low-temperature bonding technique. The process has been successfully validated through the production of hybrids combining ALTIROC3/A and LATIC2 ASICs and matching LGAD sensors, achieving a connection yield of up to 100%.
In summary, the development of ACA/ENIG-based and gold-stud/epoxy-based single-die hybridization technologies offers reliable, flexible, and affordable alternatives to traditional wafer-level processes. These techniques significantly enhance access to hybrid pixel detector technologies for R&D projects and small production runs, supporting the advancement of high-resolution tracking and timing detectors for future collider experiments.