Speaker
Description
The Barrel Calorimeter Processor (BCP), based on ATCA blade architecture, has been developed for the readout of the electromagnetic calorimeter (ECAL) and hadron calorimeter (HCAL) subdetectors. The BCP supports 120 optical receive channels of up to 25 Gbps, 72 optical transmit channels of up to 25 Gbps, an AMD XCVU13P UltraScale+ FPGA, and an embedded AMD Zynq UltraScale+ SoC. The production candidate BCP V2 is currently undergoing testing. This presentation highlights key testing results, such as high-speed link performance, power integrity, and clock phase alignment, as well as lessons for the design of the upcoming production BCP V3.
Summary (500 words)
For the phase-II upgrade of the CMS electromagnetic calorimeter (ECAL) to support the high-luminosity upgrade of the LHC (HL-LHC), the detector granularity will increase 25 fold by returning sampled data from each lead tungstate crystal instead of the current scheme which returns an aggregated value collected from a 5x5 block of crystals. In addition, to better handle background suppression, the sampling rate will increase 4 fold from about 40 MHz to about 160 MHz, synchronous to the LHC clock. This roughly 100 fold increase in data from the detector requires back-end electronics to be upgraded to handle this large data capacity. The upgraded back-end electronics will also support the Level-1 trigger latency increase from about 4 µs to a maximum of 12.5 µs and the trigger rate increase from 100 kHz to an average of 750 kHz. Additionally, the synchronous clock delivered to the detector electronics from the back-end has a tightened specification of less than 10 ps of RMS jitter and phase skew in order to support the overall timing resolution precision of 30 ps.
The Hadron Calorimeter (HCAL) underwent front-end electronic upgrades in the previous upgrade phase along with back-end upgrades based on the microTCA architecture. In order to support HL-LHC, the HCAL back-end requires electronics upgrades to handle the increased data rates and Level-1 trigger latency.
This new back-end platform for ECAL and HCAL is called the Barrel Calorimeter Processor (BCP). Initially, only the CMS barrel section of ECAL and HCAL were to be supported by the BCP, hence the condensed name, Barrel Calorimeter. However, HCAL Forward and HCAL Outer will also be supported.
The design of the BCP is an Advanced Telecommunications Computing Architecture (ATCA) blade that adheres to the base specification PICMG 3.0 R3.0. It contains 18 slots for Samtec FireFly optical transceivers of different flavors, some of which are capable of 25 Gbps transmission rates, of which the BCP supports. The primary digital computing engine is hosted by an AMD Xilinx Virtex UltraScale+ VU13P FPGA that interfaces directly with the FireFly. An embedded linux system-on-chip (SoC) computer, based on the Zync UltraScale+, handles the external interface to the FPGA and an embedded SoC microcontroller, based on Zynq 7000, continuously monitors the blade's health and can automatically shutdown voltage rails if any voltages or temperatures are measured outside their critical thresholds.
A demonstrator version of the BCP, the BCP V1, has previously been designed and five boards have been built and are currently in service in development test stands and test beam campaigns. A production candidate design, the BCP V2, has also been designed and built. It is currently being tested in order to verify its operation and that it meets specification. The tests and following results that will be presented here include high-speed links, up to 25 Gbps, eye diagrams, high-speed links bit error rate, power integrity, thermal management and clock phase alignment. Additionally, lessons learned from the V2 design and proposed design changes for the final production version, BCP V3, will be discussed.
