6–10 Oct 2025
Rethymno, Crete, Greece
Europe/Athens timezone

FPGA-Based Real-Time Waveform Classification and Reduction in Particle Detectors

9 Oct 2025, 16:00
16m
Rethymno, Crete, Greece

Rethymno, Crete, Greece

Aquila Rithimna Beach Crete, Greece
Oral Module, PCB and Component Design Modules

Speaker

Dr Ilja Bekman (Forschungszentrum Juelich GmbH (DE))

Description

The SHiP SBT self-triggered readout will process SiPM sum signals sampled at 800 MSPS and 12 bit resolution to extract calorimetric particle hit information.
A waveform classification is being deployed on the readout FPGA to reduce the volume of transmitted data. The classification divides events into expected signal, expected noise or containing unexpected features applying different degrees of compression. In this study, we consider LUT-based neural-networks and address challenges of NN layout, footprint and performance.
Preliminary planning indicates significant data reduction, easing constraints on infrastructure.

Summary (500 words)

In Search for Hidden Particles (SHiP) - a fixed target experiment - the SBT subsystem is to utilise approximately 900 liquid scintillator cells, each to be equipped with two light detectors; each light detector to be segmented into eight groups of five SiPMs to detect particles crossing the cells or low light-yield events within the cells.
Data acquisition for each detector will be generally self-triggered assigning each event a timestamp to analyse coincidences with other events of other detectors and other subsystems in offline clusters.
The SiPMs signals are proposed to be shaped by a dedicated chip resulting in eight fast digital threshold signals – to extract time-over-threshold and first hit time - as well as two analogue sum signals with low and high gain.
The analogue sum signals are to be digitized at sampling rate of about 800 MSPS and 12 bit resolution to extract calorimetric hit information.
High maximum event rates per cell are threshold-dependent, with current estimation of up to 0.6 MHz and total event rate of about 30 MHz, data about which has to be transmitted for offline processing.
The digital frontend of the readout will be using a commercial FPGA SoC and firmware implementation is the subject of this study.

A waveform classification on an FPGA is under development as a part of the digital data processing in order to reduce the transmitted data volume.
The classification has to label each event as one of three cases: expected and typical SiPM waveform - to be compressed; expected noise event - to be discarded; or waveform containing unexpected features that has to be transmitted in full.
This classification in real time and at an early stage is essential to keep the processing chain efficient.

In this study, we compare the waveform classification of cut-based and machine learning (ML) implementations.
For the ML, the LUT-based, unclocked architectures are considered since they offer latency in the order of few 10 ns to process waveforms in real time.
Among the challenges of the NN-based implementation is the 1 kbit size of the input, requiring control of the connection sparsity of the hidden layers and an appropriate downsampling.
Furthermore, the labeling task may warrant a splitting into several narrowly tasked networks with individual requirements rather than creating one classifier network.
The quantization-aware training and performance evaluation will be performed on cosmic muon data resembling final data taking conditions and are expected to evolve with a real data from commissioning and production.

Preliminary planning of the hit data composition generated at the FPGA is about 2.2 kbit including both gain waveforms and timing data; this can be reduced to calorimetric features of the waveform and transmitted alongside the timing data to about 320 bit. With a mix of compressed and raw events resulting from the classification performance the total data bandwidth of the subsystem can be reduced by at least 40-50 percent resulting in more relaxed constrains on the online and offline infrastructure.

Keywords: data acquisition architecture, edge computing, neuromorphic computing

Authors

Mr Chimezie Eguzo (Forschungszentrum Juelich GmbH (DE)) Dr Ilja Bekman (Forschungszentrum Juelich GmbH (DE))

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