Speaker
Description
As part of the CMS phase-2 upgrade, the Serenity collaboration is developing Serenity-S1, a versatile FPGA-based processing card using the ATCA form factor. Widely adopted by various subdetector systems for the back-end data processing, a total of 777 boards are planned for production. This contribution presents the Factory Acceptance Test (FAT) designed for automated and efficient board commissioning directly at the factory, reducing test time to as little as 10 minutes. Initial results of the extended pilot production are shown including feedback from the assembler and subsequent improvements to the FAT.
Summary (500 words)
The upcoming high-luminosity LHC (HL-LHC) upgrade necessitates replacing and updating several sub-detectors within the CMS experiment. For this, the Serenity collaboration has developed the Serenity-S1, a versatile FPGA processing card based on the ATCA form factor, meeting the back-end processing requirements of multiple sub-detector systems. The card is based on a modular approach, including a space-optimised service area that provides the ATCA infrastructure, advanced board management features, and a performance-optimised payload area featuring an AMD Virtex Ultrascale+ VU13P connected to 124 bidirectional high-speed links. In total, about 777 of these cards will be produced for multiple CMS detectors.
An efficient and reliable quality assurance (QA) strategy is required for production, which extends the automated optical inspection performed by the assembly company. To achieve this, a three-stage approach is used. First, a Factory Acceptance Test (FAT) is performed directly at the assembler, allowing for short repair cycles and ensuring that every board shipped to CERN is functional and configured. Upon arriving at CERN, the FAT is repeated, the mechanical parts are added (i.e., heatsinks, supports, and covers), and finally the cards are subjected to an extended version of the FAT denoted as the User Acceptance Test (UAT). Afterwards, the boards are distributed to the different sub-detectors where the optical parts are added and a final burn-in test is performed.
The FAT procedure starts with an impedance check, via dedicated test headers, of all power rails to ensure the board can be powered safely. Next, a slow control (e.g., Ethernet, I2C, PMBUS) test of the Serenity-S1 is performed, using a microcontroller for the ATCA service area and an AMD Zynq-based SoM for the payload area. During this test, the power supplies of the board are also configured to the correct voltages, independently verified, and the jitter cleaners are set to the desired frequencies. Afterwards, the test is extended to include the FPGA with a custom bitfile, which checks the clock distribution and high-speed SerDes connectivity using copper loopback cables in the optical sockets. Finally, a test report is created, which is automatically uploaded to a database.
Our approach leverages Python APIs of the board management software tools (SMASH and EMP-Toolbox), integrating them into Pytest environments to structure comprehensive test runs. Initially, a Jupyter notebook provided a graphical user interface (GUI) as the central interface to the test stand, including equipment, and offered an intuitive way to monitor and control the testing process. This interface was later replaced with a simplified button-based GUI to further streamline usage.
This talk will explain the rationale behind the 3-stage testing process, of which the FAT is the 1st stage, including the compromises made and the resulting benefits/risks. It will detail the implementation of the FAT for the Serenity- S1 board and present the results and lessons learnt from using it during the extended pilot and pre-production phases.