Speaker
Description
We present a novel 10 Gbps wafer-level testing system to characterize stitched Monolithic Active Pixel Sensors (MAPS) for ALICE ITS3 and ePIC SVT. Using a custom probe card and a 12-inch wafer-probe station, we demonstrate, for the first time in high-energy physics, 10 Gbps link characterization directly on wafer. Signal integrity was validated via bit error rate testing (BER < 10⁻¹²) and <70 ps jitter using an Enclustra Mercury FPGA. The setup, including FPC and VTRx+ optical readout, enables full-rate sensor evaluation prior to dicing. Probe card design and mechanical/electrical studies for reliable contact are also described.
Summary (500 words)
Pixel detectors for next-generation high-energy physics experiments must operate at increasingly high data rates (23.04 Gbps produced by MOSAIX, with higher rates expected in the future) to meet the demands of upgraded luminosity and triggerless readout architectures. Monolithic Active Pixel Sensors (MAPS), particularly stitched designs like MOSAIX, developed for ALICE ITS3 at CERN and also adopted by the ePIC SVT at Brookhaven’s EIC, include embedded serializers capable of operating at 10.24 Gbps. Wafer-level testing of these high-speed components is critical due to the high cost of integrating defective sensors, yet traditional cantilever probe techniques are limited to sub-GHz operation. The use of vertical probing techniques, coupled with high-speed multilayer organic support, allows probe cards to operate up to tens of GHz.
A dedicated high-speed wafer-level test infrastructure has been designed specifically for the needs of both the ALICE ITS3 and ePIC SVT projects. The system enables testing of stitched, ultra-thin MAPS directly at wafer level and at full link speed. At its core is a 12-inch semi-automatic wafer-probe station equipped with a custom-designed vertical probe card, optimized for probing 50 μm-thin substrates. The probe card features differential impedance-matched (100 Ω), length-matched traces with minimized parasitics, ensuring minimal signal distortion. Proper termination was implemented on the measurement equipment, and all connections used SMA-rated high-frequency cabling via an FMC breakout to an Enclustra Mercury FPGA module.
As a demonstrator, we used NKF7, a standalone 10 Gbps serializer chip fabricated as part of the MOSAIX development. Wafer-level testing of 50 NKF7 chips and multiple full wafers validated the setup’s performance: bit error rates were consistently below 10⁻¹², and jitter measurements remained under 70 ps. The high-speed data stream was converted to optical and transmitted to the FPGA, confirming end-to-end link integrity and system-level compatibility.
Mechanical studies were also a critical part of development. Both non-destructive optical metrology and destructive Focused Ion Beam (FIB) imaging were used to analyze probe marks and assess the interaction between probe needles and the metal pad stack. In particular, the contact surface was examined under a range of forces and inclinations of the needles with respect to the pads. Different needle families are being tested. These results directly informed the selection of an optimal probe needle family, ensuring consistent contact force, minimal pad damage, and high signal quality.
To our knowledge, this is the first demonstration of full-speed, wafer-level testing of stitched MAPS in high-energy physics. The infrastructure is ready for deployment in pre-production quality assurance pipelines for both ITS3 and SVT, and sets a foundation for future large-volume MAPS developments exceeding 10 Gbps. While at the time of writing the setup was tested only with a 10 Gbps serializer, the probe card was designed to sustain a load of 16 GHz on the RF needles.