Speaker
Description
During the High Luminosity LHC, the instantaneous luminosity is expected to reach a peak of $7.5 x 10^{34} cm^{-2}/s$. The current CMS Inner Tracker will have to be entirely replaced to withstand a significantly higher data rate while operating in an harsher radiation environment.
The demanding requirements for the upgrade are met through the use of 65 nm CMOS technology readout chip and a smaller pixel size for the sensor, both integrated into a serial powering chain.
This work presents the Quality Control procedure developments and the results that were used to evaluate the performance of the pixel module prototypes.
Summary (500 words)
During the High Luminosity LHC (HL-LHC), the increase in luminosity will lead to a significantly higher number of interactions per bunch crossing. As a consequence, the pixel detector, being the closest component to the interaction point, would be unable to operate under these conditions. Stringent requirements are imposed for the upgrade, such as radiation tolerance, a large memory buffer and a high readout speed. All those prerequisites are satisfied by a readout-chip (ROC) realized in 65 nm CMOS technology bump bonded to a sensor featuring a pixel size of $25\times100\mu m$.
In addition to that, an entirely new detector layout will picture the pixel modules forming a serial powering chain to meet the power consumption demand. Each unit of the chain, consisting of either dual or quad-chip modules, will be sharing the same input current. This baseline choice for the Inner Tracker upgrade prevents one failing chip from breaking the whole chain, and at the same to provides the necessary supply voltage to each ROC through a Shunt Low Drop Out (Shunt-LDO) regulator.
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Depending on their envisaged bandwidth, the readout-chips within a module can send data either independently or through different "master-slave" configurations. In the first case, each ROC transmits data using per-chip high-speed channel. The second configuration allows one or more chips to serialize differential data inputs from other chips along with their own data, combining them into a single high speed transmission with up to 1.28 Gbps, reducing the amount of cables and therefore the power consumption.
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To evaluate the performance of the new pixel modules, a Quality Control (QC) test flow has been developed, optimized and automated on several prototypes and serves as a key part of the grading process for production modules. Individual tests of the readout-chip and the sensor are included in the QC procedure together with full-module functionality and data transmission tests. The procedure begins with a powering test of the SLDO circuit of the ROC and the investigation of the breakdown voltage for the silicon sensor. Once the pixel module is fully assembled, a critical step is the verification of its correct functionality and data transmission capability. All pixels are calibrated to produce a uniform response to identical input signals, identifying non-performing or faulty pixels. Lastly, the integrity of the bump-bond connection between sensor and readout-chip is assessed using different techniques.
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This talk presents the first QC results of the prototype modules that were crucial in defining the selection criteria and guiding the improvements and modification to the pixel module design. Additionally, the same specifications were used as benchmarks for the Quality Control results of the finalized design to confirm that, despite minor design adjustments, it continues to meet the upgrade requirements. The QC test flow is finally applied to production modules to qualify their behavior against the upgrade requirements and to evaluate their performance based on how closely they align with those standards.
