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Description
The dual-radiator RICH detector of the ePIC experiment at the future Electron-Ion Collider will use more than 300 thousand SiPM pixels as photosensors, organized in more than 1000 Photodetector Units (PDU). Each PDU is a $\sim$5x5x12 cm$^3$ module that includes 4 custom ASICs, connected to 256 SiPMs, and a FPGA-based card (RDO) controlling the readout. Considering dRICH moderately hostile radiation environment, this work discusses the results of proton irradiation tests on key components of the RDO for radiation cumulative and single event effects. The tested components were validated for the RDO development, but SEU mitigation techniques are needed as expected.
Summary (500 words)
A maximum instantaneous flux of $\phi _5 (h>20\text{ MeV}) \approx 700 \text{ Hz/cm}^2$ and a TID$_5$ $\approx$ 2.3 krad are estimated for the dRICH electronics region, considering a 1000 fb$^{-1}$ integrated luminosity and a 5x safety factor. Since the RDO readout card is included within the dRICH sensor area, its electronic components must be evaluated for sensitivity to TID and the occurrence of SEUs and possible SELs.
At the proton irradiation facility in Trento, three key components of the RDO were tested: the main readout AU15P SRAM-FPGA from AMD, the Si5326 clock multiplier from Skyworks and the ATtiny817 power microcontroller from Microchip. A cumulative TID was integrated on each device and the Mean Time Between Failures (MTBF) was estimated, considering the full device memory and the total number of devices within the dRICH detector.
The Si5326 and ATtiny817 evaluation boards were aligned on a proton beam of 100 MeV kinetic energy and with a 10$^8$ Hz/cm$^2$ flux. A TID = 42 krad was integrated on the Si5326 chip, no SELs or damages were seen and a MTBF = 3.8 h was estimated for its configuration memory. The jitter stability of the generated output frequency was also tested and no strong deviation was observed. The ATtiny817 chip stopped working at TID = 23 krad, without any evidence of SELs, and both its SRAM and FLASH registers were checked, estimating MTBF = 4.0 h and $\text{MTBF} > 43$ h.
The ALINX AXAU15 board, integrating the AU15P FPGA, was aligned on a proton beam of 70 MeV kinetic energy and with a 10$^6$-10$^7$ Hz/cm$^2$ flux. The FPGA was programmed for SEU self-detection, using a firmware based on a 1 Gb/s Ethernet link that implements IPbus protocol to check the Flip-Flop memory, the Configuration RAM and Block RAM registers. The main software was developed to search for errors within the different memory locations and act accordingly. A TID = 6.4 krad was integrated, without SELs or damages, and a MTBF was estimated for each type of memory: 2.5 min for CRAM, 2.1 min for BRAM and a $\text{MTBF} > 3.6$ min for the FF memory.
All devices were validated for a TID exceeding $\text{TID}_5$ and no destructive events were observed for $\text{TID} < \text{TID}_5$. However, the MTBF analysis indicates the need for SEU mitigation techniques. Therefore, the Si5326 and ATtiny817 chips will implement mitigation at the configuration level, while the AU15P firmware will handle SEUs affecting BRAM and FFs. For SEU mitigation of the AU15P CRAM, the RDO will host a Microchip MPF050T FLASH-based FPGA to perform scrubbing through a QSPI FLASH memory on board (the MT25QU01 from Micron).
The RDO card will also include other components as: a second Si5319 clock multiplier from Skyworks, the VTRX$+$ optical link from CERN, two LTM4709 LDOs and a LTC3203 step-up charge pump from Analog Devices. These components are planned for evaluation in future irradiation campaigns. Meanwhile, the RDO card is currently in production and will also undergo dedicated radiation testing.
