Speakers
Description
Results are presented for the measurement of Single Event Upset (SEU) rate and recovery demonstration for the Kintex-7 FPGA on Thin Gap Chamber (TGC) readout boards for the ATLAS experiment at HL-LHC. The readout boards were installed on the TGC detectors in the ATLAS detector area. We observed 133 single-bit and 5 multi-bit SEU errors in the configuration memory of the Kintex-7 FPGA during Run-3 data taking of pp collisions at 13.6 TeV with an integrated luminosity of ~90 /fb. All the errors were automatically recovered by the soft error mitigation controller implemented in the Kintex-7 FPGA.
Summary (500 words)
Results are presented for the measurement of Single Event Upset (SEU) rate and recovery demonstration for the Kintex-7 FPGA on Thin Gap Chamber (TGC) readout boards for the ATLAS experiment at HL-LHC. The TGC readout boards will be upgraded toward the HL-LHC planned to be operational from 2030. The new readout board integrates a Kintex-7 FPGA as a core of the board, to collect detector signals from 256 channels, to send them to the off-detector boards via serial data transmitters, and to provide discriminator threshold for the frontend electronics mounted on the chambers. In total 1434 readout boards will be installed and they should be operational for more than ten years to collect data of an ultimate integrated luminosity of 4000 /fb.
Despite the tremendous advantages of the Kintex-7 FPGAs on the flexibility of the logic, the stability of the serial data transfer by dedicated transceivers, and relatively high tolerance against the Total Ionizing Dose, the SRAM-based nature of the configuration memory provides challenges for the failures due to SEUs. The flux of hadrons with kinetic energy greater than 20 MeV at the locations of the TGC readout boards for an integrated luminosity of 4000 /fb was estimated to be 0.5 x 10^11 /cm^2. The TGC system is designed to detect the SEUs on configuration memories of the Kintex-7 FPGA by the Soft Error Mitigation (SEM) controller implemented in the Kintex-7 FPGA. The errors recoverable by the SEM controller are to be automatically recovered by the SEM controller, and unrecoverable errors by the reconfiguration of the Kintex-7 FPGA using flash memories, which is initiated from external boards.
In this work, a TGC readout board from series production toward HL-LHC was installed on the TGC detector in the ATLAS detector area, at a distance ~13 m from the beam axis and ~13 m from the interaction point in the beam direction. The test was performed from 9 April to 5 May (1st round) and from 8 June to 10 October (2nd round) in 2024. The delivered integrated luminosity is 11 /fb and 80 /fb for the 1st and 2nd rounds, respectively. The SEU errors were detected by the SEM controller, and automatic recovery was demonstrated. The counts of the errors and recoveries were read out via optical fibers to an off-detector board.
We observed 133 single-bit and 5 multi-bit errors in the configuration memory of the Kintex-7 FPGA and all the errors were successfully recovered. Figures 1 and 2 show the observed cumulative SEU counts depending on the delivered integrated luminosity for the two periods. All the errors were observed during the collision runs, and recovered automatically by the SEM controller. As the SEM controller covers the corrections of all single-bit errors and multi-bit errors when errors are distributed one per frame, the observed multi-bit errors are considered to be distributed one per frame. The cross section calculated by assuming the estimated flux of hadrons with kinetic energy greater than 20 MeV was ~ 2 x 10^-15 cm^2/bit.
