Speaker
Description
The contribution is focused on the new readout electronics for the µ-RWELL-based detectors that should be installed at the LHCb upgrade2 muon system. It is based on the FATIC (FAst Tuning Integrated Circuit) ASIC, providing charge and timing measurements of acquired signals. A first version of the chip, readout and controlled by a custom FPGA board, has been tested both in laboratory and during a beam test with µ-RWELL-prototypes and results are discussed. A new FATIC version with dead time reduced by a factor 10 is being designed thus improving the chip performance at the LHCb upgrade2 expected signal rates.
Summary (500 words)
In order to exploit the physics opportunities due to the increase of the LHC luminosity up to 10^34cm^-2s^-1 foreseen at the Run 5, the LHCb Collaboration is proposing the upgrade 2 of the apparatus. The upgraded LHCb muon system aims at sustaining expected rates of incident particles up to about 1MHz/cm2 and new detectors with improved high-rate capabilities based on the µ-RWELL (micro-Resistive WELL) technology will therefore be installed in the most exposed inner regions. The baseline option for the readout electronics of these detectors is presented in the contribution. It is based on the FATIC chip, designed for the processing of signals with sub-ns duration and charge content at the level of 1fC readout from the Fast Timing Micropattern (FTM) detectors. The FATIC chip reads out 32 analog channels, each one equipped with a charge sensitive amplifier (CSA) connected to two branches providing charge and timing measurements with 100ps resolution. The FATIC analog section is configured and controlled by a digital unit providing data serial transmission at 640Mbps.
A first version of the FATIC chip has been installed on different detector prototypes for the LHCb muon system, namely pure µ-RWELLs and hybrid chambers (G-RWELLs), composed of µ-RWELLs integrated with the addition of a GEM (Gas Electron Multiplier) foil. These detectors readout by FATIC ASICs have been both tested with cosmic rays and exposed at muon beam in 2024. The setup assembled for the tests includes a custom readout board, i.e. MOSAIC (MOdular System for Acquisition, Interface and Control) equipped with a Xilinx Artix7 FPGA providing the control of the FATIC chip and data transmission via Gigabit Ethernet. A dedicated software has been developed for data acquisition performing also the configuration and monitoring of FATIC and MOSAIC boards. The system under test showed promising results that are discussed in the presentation both with µ-RWELLs and with G-RWELLs, reaching global detector efficiencies above 95% and time resolutions at the level of few ns.
The increase of the signal rate per channel up to 700kHz/ch expected at the LHCb upgrade 2 muon system, strongly affects the dead time required for the readout electronics. The current FATIC chip has a dead time of about 1μs, mainly driven by the CSA, which should be reduced up to 100ns in order to guarantee efficient operations at the expected rates. An improved version of the FATIC chip with the required dead time is thus being designed for the LHCb µ-RWELLs and is presented in the contribution. The simulation reliability of the new FATIC version is being improved by performing a detailed study of signals produced by the µ-RWELLs.
