Speaker
Description
The CMS MIP Timing Detector (MTD) will deliver a timing resolution of ~30 ps at the beginning of High Luminosity LHC. A unified MTD data acquisition (DAQ) system has been developed to provide data readout, as well as comprehensive control and monitoring functionalities. Precision timing distribution is critical for ensuring stable synchronization and robust calibration procedures. The unified DAQ system spans both barrel and endcap, managing a large number of high-speed optical links, supporting millions of readout channels. The system is powered by Serenity ATCA boards with AMD/Xilinx VU13 FPGAs and built on custom, modular firmware and software frameworks.
Summary (500 words)
The MIP Timing Detector (MTD) is an integral component of the Phase-2 upgrade of the CMS experiment at the High-Luminosity Large Hadron Collider (HL-LHC). It is designed with a primary objective of achieving a time resolution of ~30 ps at the beginning of operation, across a broad energy range. This level of temporal resolution is critical for mitigating the effects of high pileup expected during HL-LHC and contributes to improved vertex association, particle identification, and overall event reconstruction performance. The MTD comprises two distinct detector subsystems: the Barrel Timing Layer (BTL) covering up to eta=1.5, based on LYSO:Ce scintillators coupled to SiPMs read out by the TOFHIR ASIC; and the Endcap Timing Layer (ETL) extending up to eta=~3, which employs Low Gain Avalanche Detectors (LGADs) read out by the ETROC ASIC. Despite the differing sensor technologies and readout architectures, the DAQ system is implemented using a unified design that provides a consistent interface for both detectors. The BTL and ETL are equipped with 864 and 1688 optical DAQ/control links, respectively, moving data from on-detector to off-detector at 10 Gb/s for each link. These links handle data transmission, slow control, and synchronization across close to 9,000,000 readout channels.
A key feature of the DAQ system is its integration of data readout with comprehensive slow control and monitoring of the on-detector electronics. The DAQ is based on Serenity ATCA boards featuring AMD/Xilinx VU13P FPGAs and is supported by a custom modular firmware and software stack. This architecture enables configurable data flow control, front-end configuration, synchronization and monitoring, ensuring stable and efficient operation. Precision timing performance is maintained through an embedded clock distribution network based on lpGBT ASIC. The system employs calibration methods that exploit the detector phi- symmetry and monitor clock phase alignment to correct for channel-dependent clock shifts, wander, and low-frequency jitter. These procedures are essential for achieving channel-level timing stability and maintaining detector-wide synchronization over extended data-taking periods. The DAQ system is built to manage the high data throughput and stringent timing constraints imposed by the MTD design. Its modular and scalable implementation simplifies integration with CMS global systems and allows for efficient operation, commissioning, and maintenance in local applications. The common DAQ infrastructure across BTL and ETL minimizes complexity while accommodating the distinct requirements of the two subsystems. In summary, the MTD DAQ system provides the necessary infrastructure to support precision timing measurements at HL-LHC. It integrates readout, control, and synchronization in a scalable and unified framework capable of handling diverse detector technologies. The system's architecture enables reliable operation and precise timing performance, contributing to the broader goals of the CMS Phase-2 upgrade in terms of pileup mitigation and enhanced event reconstruction capabilities. This presentation will provide an overview of the DAQ firmware and software, describe the characterization of the precision clock distribution system, and present initial performance measurements from the fully integrated BTL readout chain. Additionally, the calibration procedures embedded within the DAQ system, which are essential for maintaining long-term timing precision, will be discussed.
