Speaker
Description
The MIP Timing Detector (MTD) is a key component of the CMS Phase-II upgrade for the High-Luminosity LHC. It includes a barrel (BTL) and endcap (ETL) timing layer. The BTL uses LYSO:Ce scintillating crystals coupled to SiPMs, read out by TOFHIR2 ASICs. The system targets a time resolution of 30 ps at the start of HL-LHC operation, degrading to 60 ps by the end due to radiation damage. We present an overview of the BTL readout electronics design and recent results from testing the production version of the TOFHIR2 ASIC and full system integration tests.
Summary (500 words)
A central component of the CMS Phase II Upgrade is the construction of a new MIP Timing Detector (MTD), designed to measure the time of arrival of charged particles with high precision. The Barrel Timing Layer (BTL), a thin, standalone detector, forms the barrel section of the MTD. It consists of LYSO:Ce scintillating crystal bars read out by silicon photomultipliers (SiPMs) at both ends, totaling approximately 330,000 channels. Developing and producing a dedicated readout electronic system has been essential to achieving the target timing performance.
The core of the readout is the TOFHIR2 ASIC, with each chip reading signals from 32 SiPM channels. Each channel includes signal amplifiers, leading-edge discriminators, time-to-digital converters, charge-to-digital converter, 40MHz 10-bit SAR ADC, and local control logic. Pulse shaping in the post-amplifiers helps mitigate the effects of SiPM dark count rate induced by radiation damage and of pile-up of LYSO pulse tails. TOFHiR2 meets the requirements for timing resolution - 30 ps at the beginning of HL-LHC and up to 60 ps by the end - and provides signal amplitude measurements with better than 5% precision. It supports an MIP rate of 2.5 MHits/s while maintaining a static power consumption below 15 mW per channel. Test results from the production version, TOFHiR2C, will be presented.
A Readout Unit (RU) is the building block of the BTL detector electronics, and includes twelve Front-End (FE) boards, each equipped with two TOFHIR2 ASICs to handle data from 64 SiPM channels and two ALDO2 ASICs for power and bias voltage regulation. The FEs connect to a Concentrator Card (CC), which hosts two fully-redundant low-power Giga-Bit Transceivers (lpGBT), and two Versatile Link Plus (VTRx+) chips for high-speed optical communication with the off-detector Data Acquisition (DAQ) system. The uplink operates at 10.24 Gb/s and the downlink at 2.56 Gb/s, enabling bi-directional data transfer at high bandwidth. Each TOFHiR2 ASIC sends data through two 320 Mb/s E-links to the lpGBTs, while configuration data and control signals are received at 80 Mb/s. Two RAFAEL ASICs distribute the 160 MHz clock to the TOFHiR2s.
Power distribution and monitoring are critical for reliable operation in the LHC radiation environment. Power Converter Cards (PCC), in conjunction with ALDO2 voltage regulator ASICs, provide the necessary power regulation to the FEs and the TOFHIR2 chips, as well as the SiPMs bias-voltage. The GBT-SCA chips on the CC monitor low voltages, temperatures, and SiPM bias currents to ensure stable operation.
In total, the BTL system comprises 432 RUs, organized into 72 trays, and is engineered to fit within the limited radial space of the CMS detector. The first production trays have recently been assembled, and performance results from system integration will be presented. Additional validation of the readout electronics is planned at an upcoming test beam campaign.