Speaker
Description
The Circular Electron Positron Collider (CEPC) has been proposed to operate as a Higgs factory producing electron-positron collisions with a center-of-mass energy of 240 GeV. The muon detector of CEPC plan to use the plastic scintillators with silicon photomultiplier (SiPM) to collect the scintillation light. In this work, we report the design of a readout system based on the ASIC readout scheme to handle the multi-channel from the SiPMs. A dedicated mockup system has been built and its performance are carefully evaluated. The testing results show that this system meets the requirements of the muon detector of CEPC.
Summary (500 words)
The CEPC will measure the properties of Higgs boson, Z boson and W boson in detail, and also offer opportunity of searches for beyond standard model physics. The components of the reference detector of CPEC are vertex detector, inner tracker, time projection chamber, electromatic calorimeter, hardon calorimeter and muon detector. The muon detector is designed for high efficiency and precise muon identification, providing nearly complete coverage and a low pion-to-muon misidentification rate at high momentum. The baseline choice of the technology for the muon detector is plastic scintillator bars with SiPMs. The design of the baseline choice requires over forty thousand channels of SiPMs with good signal-to-noise ratio, excellent time resolution of about 1 nanosecond and low power consumption of electronics.
This paper presents the design of an ASIC readout system based on the MPT2321 chip for SiPMs signal process, which is a candidate of the readout system for the muon detector. The MPT2321 chip is a 32 channel ASIC for SiPMs signal processing with 12 bits ADC of 1 mV precision and 20bits TDC of 50 ps precision. It can give the charge, number of photon and arriving time of the input SiPM signal. This system has the advantage of high density, excellent time resolution, high signal-to-noise ratio and low power consumption.
A mockup system with four chips has been built up to evaluate detailed performance of this system. The mockup system consists of four ASIC boards to host the MPT2321 chip and a Xilinx KC705 evaluation FPGA board. A hardware-based network processor (SiTCP) for high-speed data transfer is employed in the FPGA board to control chip and readout data. The ASIC boards and FPGA board are connected via the FMC interface with FMC-to-HDMT converter and commercial HDMI cables.
The characteristics of the mockup system have been measured by injecting charges and connecting to the SiPMs, including gain, charge linearity, signal-to-noise-ratio, and power consumption.
The gain of the eight modes of MPT2321 has been determined by injecting charges to the chip with 47 pF and 1 nF capacity. A SiPM array is connected to the inputs of the MPT2321 chip to evaluate the performance of the mockup system with SiPM. The charge spectra are measured with the high gain mode with an over-voltage of 2 V. The signal-to-noise ratio is measured with the HG scale by scanning over-voltages of SiPM from 1 V to 4 V. The power consumption of the MPT2321 chip is measured by monitoring the current of each power supply of the chip, including 1.8 V and 3.3 V in the analog domain, and 1.8 V and 3.3 V in the digital domain.
The testing results show that the performance of the MPT2321 chip can meet the key requirements of the baseline design of the muon detector of CEPC. This system also provides a reference and guidance for other relevant applications, such as neutrino experiment at low temperature.
