Speaker
Description
To enhance solid-angle coverage and detection efficiency in synchrotron radiation experiments, the HEPS/PAPS Detector System Project Team at the Institute of High Energy Physics has developed prototype SDD array systems, consisting of 5 and 20 hexagonal-pixel elements, in response to the future requirements of the High Energy Photon Source (HEPS), a fourth-generation synchrotron facility currently under construction in China. The self-developed 20-unit array detector system, with complete development of the sensor, front-end ASICs, and readout electronics, has been tested using a 241Am source, achieving an energy resolution of 300 eV at 13.96 keV (-40 °C).
Summary (500 words)
The Silicon Drift Detector (SDD) is widely used in spectroscopic applications due to its excellent energy resolution and high count rate performance. To improve solid-angle coverage and detection efficiency in synchrotron radiation experiments, considerable efforts have been directed toward the development of array SDD systems. The HEPS/PAPS Detector System Project Team at the Institute of High Energy Physics has been developing SDD array systems in response to the future requirements of the High Energy Photon Source (HEPS), a fourth-generation synchrotron facility currently under construction in China. Two prototype SDD array systems, consisting of 5 and 20 hexagonal-pixel elements, respectively, have been designed and implemented, with each pixel offering an effective area of approximately 10 mm². The detector system employs custom-designed 8-channel ultra-low-noise ASICs based on switch-reset charge-sensitive preamplifiers for signal readout, achieving an equivalent noise charge (ENC) better than 5 electrons at a shaping time of 1 μs and –20 °C. The signals are transmitted via high-density coaxial cables to the back-end readout electronics. The multichannel readout system integrates 16-channel, 65 MHz ADCs and a Xilinx Kintex-7 FPGA on a single board to enable high-speed data acquisition and processing. Parallel signal processing and data transmission are supported across all channels. A digital filtering-based pulse shaping algorithm is implemented to ensure high processing efficiency, enabling each channel to achieve a maximum count rate of 500 kcps. The self-developed 20-unit array detector system, with complete development of the sensor, front-end ASICs, and readout electronics, has been tested using a 241Am source, achieving an energy resolution of 300 eV at 13.96 keV (-40 °C). Building upon this foundation, the 5-unit array SDD detector system has been further optimized in terms of compactness and packaging, effectively reducing the wire bonding distance between the detector and the ASICs. Improvements in electronic crosstalk have also been achieved, and testing of the system is currently underway. In the next phase, efforts will focus on optimizing sensor performance and refining the signal processing algorithms to further enhance energy resolution and count rate, with the goal of promoting broader application in various detection scenarios.
