Speaker
Description
The TDAQ of the ATLAS experiment will be upgraded in alignment with the High-Luminosity LHC project so that the trigger rate increases from 100 kHz to 1 MHz. As the hardware muon trigger of TGC (RPC) for the endcap (barrel), we developed a Sector Logic ATCA blade consisting of a large-scale FPGA, AMD Virtex UltraScale+, and 10 Gbps optical transceivers. In two prototyping phases, we evaluated the prototype boards, especially regarding the power management, the fixed clock phase alignment, and the inter-system test. Consequently, we established the final design for mass production in 2027. These results will be presented.
Summary (500 words)
The Sector Logic (SL) board will be replaced with the new design to upgrade the ATLAS Barrel
and Endcap hardware muon trigger for HL-LHC. Along with the luminosity increases, the entire
TDAQ hardware trigger rate will increase from 100 kHz to 1 MHz. As part of the TDAQ upgrade,
the new SL is designed on the concept that it gathers all the hit information from the muon
trigger chambers with wide IO throughput and processes trigger decisions on one large-scale
FPGA.
The SL board is designed as the ATCA blade and equipped with an AMD Virtex UltraScale+
FPGA (XCVU13P) and ten pairs of 10 Gbps optical transceiver modules (Samtec FireFly) in a
total of 120 transceiver links. For the slow control and environmental monitor, the AMD Zynq
UltraScale+ MPSoC and the CERN-IPMC are embedded on the board. To handle the full muon
trigger chambers, we plan to produce one hundred boards in total. For the endcap muon trigger,
one SL board handles 1500 Gbps readout from the chamber's hits data at maximum. The hit
data is processed by the frontend digitizer and the intermediate readout board, which aligns the
signal timing and appends timing information. The trigger latency for 10 us requires a 10 Mb
buffer. The unique requirement is the fixed latency clock tree among different carrier rates,
which is supplied by the LHC central clock and is passed through to the intermediate readout
board.
Towards finalizing the design, the second prototype boards were produced, as shown in Figure 1.
During the prototyping phase, we identified and resolved several problems in the design,
such as clock frequency planning and functions of power sequencing. Especially in the power
sequence of the board, which is one of the important points, we made different mistakes on the
first and second prototypes. Those mistakes eventually led to the concrete design.
We have evaluated the second prototype, which covers broad aspects of the hardware design,
such as the signal integrity of high-speed transceivers, the power system, the cooling
performance, and the clock synthesizer. The loopback optical link test via the Virtex
UltraScale+'s GTY and FireFly was completed for all 120 links, confirming well-opening eyes at
10 Gbps. The power lanes are managed in an order (Figure 2), and the ripple on the power
lanes to the FPGA is controlled within 10 mV for the GTY. The typical power consumption of the
SL is 100 W, and the cooling capacity for the FPGA has enough room in the actual ATCA shelf.
In parallel to the board-dedicated evaluation, we performed inter-system evaluation among the
ATLAS muon trigger. Most of the inter-system links shown in Figure 3 are verified, for example,
the MDT Trigger-Processor and the readout system by FELIX.
After these comprehensive evaluations, the board design is finalized for mass production. We
plan to produce ten boards as preproduction in 2025 and process full mass production in 2026.
We will present the design, evaluation results, and prospects, highlighting lessons learned
through the prototyping.
