Speaker
Description
Precision timing is critical for the LHCb ECAL Upgrade II to operate effectively in the high pile-up conditions of the HL-LHC. Fast waveform sampling ASICs have been identified as suitable readout electronics for achieving the few tens of picoseconds resolution required to reconstruct electromagnetic showers. To extract precise timestamps in the presence of pile-up induced background, machine learning-based methods have been developed to predict the time of arrival of analog waveforms. This machine learning model has been optimized and deployed on a Xilinx Artix-7 FPGA for testing and can be translated to radiation-tolerant PolarFire FPGAs for future ECAL integration.
Summary (500 words)
The HL-LHC upgrade will bring significant challenges to experimental physicists across all experiments at CERN. The LHCb experiment will undergo major hardware upgrades during Long Shutdown 4, aimed at increasing the total integrated luminosity to 300 fb-1 and supporting instantaneous luminosities up to 1.5×10^34 cm-2 s-1. To maintain detector performance under these demanding conditions, the Electromagnetic Calorimeter Upgrade II will implement precision timing techniques to suppress background by associating electromagnetic showers to specific primary vertices. Fast waveform sampling ASICs have been identified as suitable readout electronics to achieve tens of picoseconds resolution, enabling accurate timestamping of energy deposits under high pileup conditions.
This project focuses on developing machine learning-based timestamping methods for analog signals read out from fast waveform sampling ASICs that can be deployed on standard FPGAs. Using ECAL simulation data, neural network models were trained to predict the time of arrival of particle signals with resolutions as low as a few tens of picoseconds. These models are designed to operate on limited input data, reflecting realistic ECAL readout conditions. In particular, the SPIDER ASIC, which is currently in development for ECAL Upgrade II, samples analog waveforms in a 32-point time window and is designed to digitize only a small selection of samples per pulse, depending on the local hit occupancy. To test the capabilities of similar fast waveform sampling ASICs, the AARDVARCv3 was used as a representative device, providing sampling rates and analog storage features comparable to those planned for SPIDER. Initial testing showed that conventional timestamping methods, such as digital constant fraction discrimination, perform well for isolated signals but degrade under pileup conditions. For this reason, machine learning techniques have been developed using ECAL simulation data to model realistic detector environments and improve timestamping performance.
A simple feed-forward neural network architecture was developed, consisting of a sequence of fully connected layers optimized for timestamp regression. The first iteration of this model focuses primarily on the waveform shapes formed by single photons depositing energy in the Pb-Spacal modules of the ECAL, and accurately predicts the time that the particle hits the front of the detector with sub-30 picosecond precision. In order to minimize the amount of data that must be transmitted through the detector readout chain and to preserve signal integrity by operating on directly digitized, uncompressed waveforms, this ML-based timestamping algorithm can be implemented directly on front-end FPGAs. The model was translated into HDL using HLS4ML for real-time deployment on a Xilinx Artix-7 FPGA. The ECAL simulation waveforms were then injected into the AARDVARCv3 ASIC via an arbitrary waveform generator, and the machine learning model deployed on the FPGA achieved timestamping performance consistent with results observed during simulation studies. Although initial tests were conducted on a standard FPGA, future implementations are planned for radiation-tolerant devices, such as the Microchip PolarFire series, to meet the environmental requirements of the upgraded detector. This progression enables further studies focused on mitigating pileup effects and demonstrates that precision timestamping for high-pileup environments can be implemented on front-end FPGAs in high-energy experiments.
