Speaker
Description
We present an implementation of the digital dual mixer time difference (DDMTD) circuit in an ASIC using current mode logic (CML) and discuss how it can be used to stabilize on-detector systems to a level of less than 1 picosecond. This circuit is used extensively in high energy physics applications and other clock distribution systems to monitor clock stability using FPGAs. By using CML logic in an ASIC we have been able to optimize the design for the DDMTD application and have achieved a considerable performance enhancement over what has been achieved with logic blocks in an FPGA.
Summary (500 words)
As part of a program to push the limits of precision timing in data we are exploring methods and techniques to reach sub-picosecond timing precision in high energy physics detectors. While there are many places where this has been achieved for a few channels, this is not yet possible in a high energy or nuclear physics detector system, where there are hundreds of thousands, or more, channels. To address this problem, we have focused on the problem of distributing a reference clock with a precision of 100 femtoseconds (fs) or less, which will be an essential ingredient of any detector with a timing precision of less than 1 picosecond. Our program has been to develop the tools to measure a reference clock to this level of precision [1], and to manufacture an ASIC capable of adjusting the phase of a clock in steps of 200 fs [2]. Our original DDMTD was built with discrete high speed flip flops readout with an FPGA. With this technology we have achieved a single measurement precision of 400 fs or better, and with multiple measurements made over a period of 10 seconds we have achieved a resolution of 100 fs. We have improved this precision with new circuitry to better manage the metastability of the flip flops to achieve an improvement of approximately a factor of 10. We have used our improved DDMTD and the DCPS to stabilize a reference clock 1 km away from the source clock. This is shown in Fig 1.
Our next step is to design an ASIC that includes the DDMTD circuit and the new logic. The design of the DDMTD is complete and has been submitted to TSMC in the 65nm LP process. By using an ASIC, rather than discrete off-the-shelf electronics we have been able to optimize the design for the DDMTD application. Figure 2 shows the result of a simulation showing the resolution of the DDMTD, where a phase shift is applied to a 1.2GHz clock and the shift is measured with the chip-scale DDMTD. Our next variation of this ASIC will include the logic to manage the metastability. We will also design it to be radiation tolerant so that it can be installed on-detector, which will be essential to achieve sub-picosecond timing precision in large-scale detectors.
In our presentation we will describe the design of the ASIC, the results obtained with the ASIC, and how it could be used in a real experiment to achieve a new level of timing precision.
[1] Saradhy R, Rusack R, Frahm E, Mendes E. “A Sub-Picosecond Digital Clock Monitoring System”, J. Instrum. vol. 17, no. 3, 2024, p. CO04014.
[2] Dehmeshki, Diba, et al. “Large dynamic range digital delay with sub-picosecond precision.” J. Instrum. vol. 19, no. 4, 2024, p. C04060.