Speaker
Description
The first processing stage of the HGCAL Backend trigger primitive generator system for the Phase-2 upgrade of the CMS detector will be implemented using the Serenity ATCA platform. This processing stage is responsible for receiving and pre-processing the trigger data coming from the HGCAL front-end and is composed of several firmware blocks. This contribution will present an overview of the different firmware blocks and discuss the status of their integration and validation on pre-series Serenity boards.
Summary (500 words)
The Level 1 (L1) trigger primitive generator (TPG) system of the future Phase-2 upgrade High Granularity Calorimeter (HGCAL) of CMS is composed of two off-detector processing stages. Its role is to provide trigger primitives to the central L1 trigger in the form of 3D clusters of energy and projective tower energy sums. The first stage (Stage 1) of the TPG system receives and pre-processes trigger data (trigger cells and module energy sums) coming from the front-end electronics and time-multiplexes its output data to the second stage (Stage 2).
Four main blocks are part of the TPG Stage 1 firmware payload: (1) the data unpacker block, (2,3) the trigger cell sorting block and the partial tower block, which produce two parallel streams of data, and (4) the packer and time-multiplexing block. The unpacker block unpacks the trigger data received from the front-end and aligns all fragments for a given bunch crossing together, to allow for different latencies from different front-end modules. It also converts different front-end packet encodings into a uniform packet format for downstream blocks. The trigger cell sorting block sorts trigger cells into bins corresponding to projective regions of the detector such that they can be processed in an optimal way in Stage 2. The partial tower block sums the module energies and trigger cell energies to form partial tower energies, separately in the electromagnetic and hadronics parts of the detector. Finally, the packer and time-multiplexing block packs the resulting sorted trigger cells and partial tower energies into single packets and time-multiplexes them for transmission to Stage 2.
The TPG Stage 1 will be implemented using the Serenity ATCA platform. It will be composed of 48 Serenity boards per endcap, instrumented with one VU13P FPGA each. Each of these FPGAs are expected to handle data from about 300 front-end modules distributed over 120 input links. Several intermediate builds of the Stage 1 firmware have been produced and are being tested on pre-series Serenity boards. Among these intermediate builds, some of them integrate three of the four main firmware blocks (excluding either the partial tower block or the trigger cell sorting block), and cover the full set of input modules. A complete build is also in the process of being integrated. An overview of the different Stage 1 firmware blocks will be presented as well as the status of the Stage 1 integration and validation.