Speaker
Description
The forward Feature EXtractor (fFEX), a new ATLAS calorimeter first-level trigger subsystem, will extend ATLAS' trigger performance for jets and electromagnetic signatures in the Forward Calorimeter (FCal). Utilising the full calorimeter granularity, each processor processes ~2.3 Tbps of real-time data. It is part of the trigger upgrade for the challenging conditions in the High Luminosity LHC (HL-LHC) phase, where
a significantly increased pile-up is expected.
This presentation provides an overview of the hardware and firmware design, results of the prototype's verification and highlights fFEX's role in preparing ATLAS for the HL-LHC era.
Summary (500 words)
The forward Feature EXtractor (fFEX), a new ATLAS calorimeter
first-level trigger subsystem, will extend ATLAS' trigger
performance for jets and electromagnetic signatures in the
Forward Calorimeter (FCal). Utilising the full calorimeter
granularity, each processor processes ~2.3 Tbps of real-time
data. It is part of the calorimeter trigger upgrade which will
take place after LHC and its experiments will cease operations
in July 2026 to prepare for the challenging conditions in the
High Luminosity LHC (HL-LHC) phase, where a significantly
increased pile-up of up to 200 collisions per bunch crossing
is expected.
The fFEX system consists of four ATCA modules designed to host
FPGAs and optical modules, operating at high line rates of up
to 25.8 Gb/s. At the core of each fFEX module are two large
processor FPGAs (AMD UltraScale+ VU13P). Samtec FireFly optical
modules facilitate data transmission for the real-time data and
readout path. The control mezzanine together with a Zynq
UltraScale+ (UltraZed) manages configuration, monitoring and
slow control functionality.
Power regulators on mezzanines provide the required voltages to
numerous power rails and a dedicated mezzanine ensures proper
power sequencing. Power management is realized via the Intelligent
Platform Management Controller (IPMC). Additionally, dedicated
clock distribution circuits provide reference clocks for the
FPGAs' multi-gigabit transceivers.
To achieve optimum signal integrity for high-speed signals, the
PCB is engineered using advanced design methods and its 20-layer
stack-up utilises high-performance PCB materials to ensure best
signal quality and efficient high-current distribution.
The test programme validates the module's core functions, in
particular power delivery, clock distribution, boundary-scan (JTAG),
and main FPGA operations. It also evaluates the performance of the
optical modules and the FPGAs' high-speed links, ensuring compliance
with stringent operational requirements.
The fFEX firmware is designed to process real-time data from the
LAr Signal Processor (LASP) and transmit results to the Level-0
Global Trigger (L0Global). fFEX receives energy values on
calorimeter cell level, allowing it to fully exploit the FCal's
granularity.
On both detector sides, there is one processor per azimuthal quadrant.
For signatures crossing the processor’s core region boundary, each
processor is provided with duplicated data for overlaps, extending
its available data window to its respective half of the forward
region. Therefore each processor has to receive and process ~2.3 Tb/s
of real-time data. The high-speed links use the Interlaken protocol
to ensure both high data integrity and low latency.
Real-time data stream processing algorithms identify jets,
electromagnetic clusters, hadronic taus and compute global quantities
such as missing transverse energy (MEt) within an available processing
time of just 500 ns. The baseline for clustering is the fully parallel
sliding window algorithm, while alternative approaches, including
neural networks, are being explored for potential improvements.
This presentation provides an overview of the module design,
hard-/firmware development, and results of the first prototype's
verification and highlights fFEX's role in preparing ATLAS for the
HL-LHC era.
