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Description
Description
We present the design and first test results for SPIDER_v0, the first ASIC prototype in CMOS TSMC 65nm designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements are a time resolution of 15ps, and an occupancy up to 30% (12 Mevent/s).
SPIDER_v0 is a 2-channel waveform digitizer allowing time reconstruction by digital algorithms. The architecture is based on 2 DLLs controlling the sampling window and sampling frequency, 8 banks of 32 analogue memory cells per channel and Wilkinson A/D conversion at 5 GHz for parallel digitization with a maximal conversion time of 200ns.
Summary
The LHCb Electromagnetic Calorimeter (ECAL) will undergo a major upgrade during LS4 toward “PicoCal”, a calorimeter with a requirement to measure particle arrival time with 15ps resolution to disambiguate multiple collisions. The 2nd challenging requirement is the ability to cope with an average occupancy of 10% and up to 30% on the most exposed channels.
SPIDER (Swift Pipelined Digitizer) will be in its final version an 8-channel analogue waveform sampler and digitizer for use as a “Waveform TDC”, i.e. for reconstruction of fine arrival time by an amplitude-independent algorithm like digital Constant Fraction Discriminator (dCFD).
SPIDER_v0 (Fig. 1) is the first prototype, including 2 channels with most features of the production version, and a simplified readout interface. The prototype was submitted in February 2025.
SPIDER samples the signal in a configurable time window (Fig. 2), defined in relation with the LHC clock, and generated from the output taps of a 1st DLL (DLL1 in Fig. 1) locked to the LHC clock. This restricted sampling is permitted by the predictability of arrival time in each channel (within a variation of the order of 1ns). This feature makes sufficient a sampling depth of 32 cells per bank. The sampling array is organised in 8 banks, which constitute an event buffer, allowing to cope with the occupancy requirement by eliminating dead time within the limit of 8 full banks. In each channel, the sampling instants are controlled by a 2nd DLL (DLL2 in Fig. 1) locked to the sampling window. The sampling period is configurable from 50ps to 600ps (F=1.67GHz to 20GHz), corresponding to sampling window durations from 1.6ns to 19.2ns, respectively.
Each channel also integrates a discriminator that can self-trigger; external trigger is also available. The event trigger causes the current bank to freeze its content at the end of the sampling window, and to start a conversion as soon as possible. The conversion follows the massively parallel Wilkinson ADC principle. It involves a ramp generator with configurable slope and range (nominally 200ns for 800mV) and a 10-bit Gray counter driven by a configurable ring oscillator with 5GHz maximal frequency.
SPIDER includes on-chip calibration blocks for the determination of A/D conversion characteristics per cell and the sampling time DNL, both necessary for optimal performance.
During conversion, one or several banks are digitized. After conversion, the banks are extracted, i.e. the data are transferred from the banks to the parallel output buffers. In version 0, the extraction is handled by the FPGA via a 10-bit parallel bus@320MHz max. The final version will include a logic bloc for bank data extraction, packet formation, encoding and serialisation at 2.56Gbps (baseline scenario). Each channel will have its own serial bus and send the data in “push” mode. In “smart readout” mode, only 8 samples on the rising edge will be transmitted instead of 32 in “full readout” mode.
Capture, conversion and extraction occur in parallel in different banks, allowing to treat multiple consecutive hits.
The first test results are expected in summer 2025.
