Conveners
Logic
- Johan Alme (University of Bergen (NO))
- Andrea Boccardi (CERN)
Logic
- Johan Alme (University of Bergen (NO))
- Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))
Logic
- Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))
- Johan Alme (University of Bergen (NO))
Logic
- Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))
- Andrea Boccardi (CERN)
Next‑generation pixel‑based read‑out ASICs for high‑energy physics experiments
face demanding performance and integration requirements. A flexible, pixel‑level
simulation framework is essential to design, validate, and optimize the read‑out
architecture and its building blocks. We present a SystemVerilog/UVM
verification environment developed for the IGNITE project, a 28 nm CMOS...
The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in high-energy physics. MOSAIX, a fully functional prototype and the final development step before production, measures 266 mm by 19 mm. The chip integrates 144 independently powered pixel matrices, eight 10 Gbps transmitters, and on-chip power and data...
Recent advancements in Artificial Intelligence (AI) and AI hardware accelerators have paved the way for on-edge AI processing with many benefits such as reduced data bandwidth and increased power efficiency. Applications in harsh radiation environments could also benefit from these improvements. However, due to the complex nature of both accelerators and the AI models running on them, the...
Large aperture, high resolution, single photon imaging detectors are in high demand for future space explorations by missions
such as HABEX or LUVOIR. Yet making a TRL 10 operational detector prooved to be a very challenging endavour that takes more than
a decade. This talk will review the state of the art technology, and present more in depth an ASIC designed to cope
with the requierd...
The growing capacity of high-end FPGAs enables more powerful algorithms in high-energy physics but introduces new challenges for firmware developers. The largest AMD devices, composed of multiple silicon dies (SLRs), face data transfer timing challenges due to Vivado’s placer limitations in large designs. In particular, pipelined buses crossing SLRs often experience poor flip-flop placement,...
In its phase-2 upgrades, all of the CMS experiment's backend electronics systems are being replaced by ATCA boards featuring AMD Xilinx UltraScale+ FPGAs and high-speed optical modules. The EMP (Extensible Modular data Processor) framework provides common infrastructural firmware components, top-level designs and associated software for multiple CMS phase-2 backend boards and systems. It...
This paper presents a versatile readout system for particle detector front-end ASICs based on the AMD Zynq Ultrascale+ System-on-Chips. The system is suitable for both extensive laboratory characterization and for data acquisition at testbeam facilities. Its software-level scripting of the test procedure reduces the firmware development effort, maximizing the system reusability among different...
This work explores the use of the AMD Xilinx Versal Adaptable Intelligent Engine (AIE) to accelerate Gated Recurrent Unit (GRU) inference for latency-Constrained applications. We present a custom workload distribution framework across the AIE's vector processors and propose a hybrid AIE–Programmable Logic (PL) design to optimize computational efficiency. Benchmarking against existing FPGA GRU...
The LHCb-UpgradeI experiment has adopted a heterogeneous computing-based trigger system that relies on the reconstruction of all collision events, occurring at 30MHz. In this context, a two-dimensional FPGA-based cluster-finding architecture has been developed to reconstruct in real time hit positions in the vertex pixel detector, capable of processing $\sim10^{11}$ hits/second, and freeing...
We present a real-time hit filtering system based on Graph Neural Networks (GNNs), implemented on FPGAs for the Level-1 trigger of Belle II. The system processes raw data from 14,336 sense wires with a sustained throughput of 32MHz and sub-microsecond latency. It combines GNN inference with static graph-building logic in a latency- and resource-optimized FPGA pipeline. This work demonstrates a...
