A 512-channel beam monitor was developed to measure beam parameters at particle rates from single particles up to clinical rates (several GHz). The system is designed for silicon carbide (SiC) strip sensors for increased radiation tolerance. The sensor readout uses four 128-channel analog charge-integrators with on-chip multiplexers, complemented by ADCs and a SoC module (FPGA + CPUs). Gigabit...
LANRS (Exploration of Lattice Dynamics of Nanostructures and Active Site Structures in Iron Proteins and Batteries with Nuclear Resonance) is a ministry-funded project aimed at enabling next-generation Nuclear Resonance Scattering (NRS) experiments. These require a large detection area, ultra-high temporal resolution of a few nanoseconds, and the ability to handle high event rates immediately...
Caribou is a versatile data acquisition system developed for use in several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It combines a custom Control and Readout (CaR) board with a Xilinx Zynq System-on-Chip (SoC) running project-wide shared firmware and software stacks. Ongoing...
Over the past year, significant progress has been made in the development of a dedicated test stand designed to evaluate the signal transmission integrity of approximately ~9k electrical links used in the Inner System (IS) of the ATLAS Inner Tracker Pixel upgrade. The Quality Control (QC) method of choice is a pre-existing multi-channel FPGA data acquisition architecture that has the...
We present a flexible detector readout prototyping module based on the AMD RFSoC platform, integrating fast ADCs, DACs, programmable logic, multicore CPU and several 28 Gbps-class transceivers. Sampling at GHz rates enables full digital signal processing, simplifying analog front-ends and improving timing and compactness. Two use cases are demonstrated: a digital emulation for the NA62 Liquid...
The Belle II experiment is a collider experiment using asymmetrically accelerated electrons and positrons with the world's highest luminosity.
The experiment uses a hardware trigger system consisting of customized electronic boards called Universal Trigger and other electronics.
The trigger system has a dedicated subsystem for the drift chamber of the Belle II detector, which measures the...
Modern System-on-Chip (SoC) devices are widely applicable; several boards in the LHC Phase-2 upgrade use them. However, their growing complexity, along with the increasingly intricate firmware and software development tools, makes it difficult for developers to keep up. To address this, we propose SoCks, a modular and scalable build framework for SoC devices that introduces a new layer of...
Reliable communication and control of distributed electronics is essential for safe and efficient accelerator operations at CERN. This work presents the first application of new C++ library designed to manage Beam Loss Monitoring (BLM) acquisition electronics using Low-Power Gigabit Transceivers (LpGBT). This library enables real-time communication between tunnel-based and surface-level...
The Circular Electron Positron Collider (CEPC) has been proposed to operate as a Higgs factory producing electron-positron collisions with a center-of-mass energy of 240 GeV. The muon detector of CEPC plan to use the plastic scintillators with silicon photomultiplier (SiPM) to collect the scintillation light. In this work, we report the design of a readout system based on the ASIC readout...
ITk hybrid pixel detector consists of about 10,000 planar “quad” modules formed from 4 ASICs, (developed within the RD53 collaboration) bump bonded to a single sensor operated in serial power chains.
The flex attached to the sensor connects the ASICs to the system and provides module electrical environment while fulling the mechanical specifications.
The flex must provide a signal...
In preparation for operations at the HL-LHC, the CMS Collaboration is upgrading its endcap calorimeters with a high granularity calorimeter (HGCAL). The HGCAL back-end electronics includes two Non-Zero Suppression (NZS) boards, which dynamically disable zero-suppression in designated regions of interest. This paper presents a detailed discussion of the NZS algorithm’s principal components, and...
We present ongoing work on a Central Trigger Processor (CTP) board for the future Advanced SiPM-based LST camera of CTAO (Cherenkov Telescope Array Observatory). The system aims to implement a fully digital trigger on FPGAs, leveraging increased camera resolution to better discriminate low-energy gamma-ray events from noise. This approach seeks to enhance sensitivity while meeting CTAO-LST’s...
To enhance solid-angle coverage and detection efficiency in synchrotron radiation experiments, the HEPS/PAPS Detector System Project Team at the Institute of High Energy Physics has developed prototype SDD array systems, consisting of 5 and 20 hexagonal-pixel elements, in response to the future requirements of the High Energy Photon Source (HEPS), a fourth-generation synchrotron facility...
Hybrid pixel X-ray detectors operating in single-photon counting mode provide high spatial resolution, enhanced spectral imaging, and immunity to electronic noise. A common trend is to minimize pixel size, however, it often comes at the expense of spectral fidelity and position resolution due to charge sharing between channels. The spatial resolution can be further improved, though, by...
The Embedded Monitoring Processor (EMP) is a state-of-the-art platform based on a multi-processing System-on-Chip, developed for the upgrade of the ATLAS experiment’s Detector Control System. The EMP interfaces via high-speed optical transceivers with monitoring and control functionalities of radiation-tolerant Front-Ends. Preliminary analysis revealed limitations in throughput and CPU...
The upcoming Phase-2 upgrade of the LHC presents significant challenges for CMS Back-End electronics due to dramatic increase in trigger rate, data volume, and system complexity. The system must handle L1A rates up to 750kHz with a L1A latency of 12us. The EMP Common Readout firmware addresses these needs, as a modular and flexible system designed to unify trigger event data collection across...
The forward Feature EXtractor (fFEX), a new ATLAS calorimeter
first-level trigger subsystem, will extend ATLAS' trigger
performance for jets and electromagnetic signatures in the
Forward Calorimeter (FCal). Utilising the full calorimeter
granularity, each processor processes ~2.3 Tbps of real-time
data. It is part of the trigger upgrade for the challenging
conditions in the High...
Abstract
Performance and stability of the CMS ECAL HL-LHC readout system depends on the good functionality of the Fron-End card (FE) – an interface between on-detector and off-detector section of the readout electronics.
Series of the design-specific integration tests were performed, including dependence of the readout chain functionality on the system clock quality, recovery from the...
In the context of the HL-LHC upgrades, xTCA (Advanced/Micro Telecom Computing Architecture) is a common standard in high energy physics. To keep it is a serious candidate for future readout systems and save the previous development investments in the post-telecom era, when classical telecom vendors migrating to cloud-based solution, the new coordination with manufactures is required. PICMG...
This study addresses X-ray beam stabilization challenges in fourth-generation synchrotron radiation systems by developing an active feedback control system. Replacing passive vibration isolation, the solution integrates high-sensitivity current detection (pA-nA range) for beam positioning with piezoelectric actuators achieving nanometer-scale adjustments. The driver operates at hundreds of mA...
The CMS Level-1 Trigger scouting system, planned as part of the HL-LHC upgrade, aims to collect objects reconstructed by the L1 trigger at the LHC bunch crossing rate to perform online physics analyses. As part of this effort, the use of RDMA over Converged Ethernet is being explored to transfer data from the scouting FPGAs to servers, along with the adoption of 400G Ethernet links. A first...
The new CMS trigger system for the High-Luminosity LHC upgrade will exploit detailed information from the sub- detectors at the bunch crossing rate, allowing the Global Trigger (GT) FPGA firmware to use high-precision trigger objects. The GT will contain novel algorithms based on machine learning techniques such as Deep Neural Networks and Boosted Decision Trees to reach higher selection...
For the High-Luminosity Upgrade of the Large Hadron Collider, the ATLAS detector will receive a new silicon strip tracker. The module design utilizes readout hybrid flexes and powerboard flexes glued onto the sensor surface. In total, approximately 13,000 end-cap hybrid readout flexes and 6,000 end-cap powerboards are needed to build both end-caps of the strip detector. This contribution...
The Circular Electron-Positron Collider (CEPC), a large-scale international particle physics
facility proposed and led by Chinese scientists, centers around a high-energy circular
accelerator designed to provide electron-positron collision environments. This study
proposes a multi-channel free-space optical (FSO) communication system based on
wavelength division multiplexing (WDM). The...
The ALICE ITS3 project will upgrade the inner silicon tracker layers with wafer-scale (27cm long) MAPS bent around the beampipe. The MAPS transfers its pixel data via 10.24-Gbps differential links driving a 30cm long FPC-cable.
The NKF7 proto-chip serialises a 16-bit static input to 10.24-Gbps output with a measured Bit Error Rate (BER)<10^-15. Irradiation with 32-MeV protons gives...
AC-LGAD detectors, recognized as promising candidates for 4D tracking systems, have achieved ~40 ps timing and ~10 µm spatial resolution in IHEP's 50-µm-thick strip sensors. However, centimeter-scale devices face challenges including charge sharing, capacitance, and power consumption. This study presents structural and process optimizations—such as n+ sheet resistance tuning, metal-pitch size,...
During the High Luminosity LHC, the instantaneous luminosity is expected to reach a peak of $7.5 x 10^{34} cm^{-2}/s$. The current CMS Inner Tracker will have to be entirely replaced to withstand a significantly higher data rate while operating in an harsher radiation environment.
The demanding requirements for the upgrade are met through the use of 65 nm CMOS technology readout chip and a...
During the next LHC shutdown the LHCb-RICH subdetectors will undergo a major upgrade and their electronics chain will be redesigned. The new on-detector electronics architecture will employ bPOL12V power modules. This work presents the validation strategy and the test system, which was designed to assess the performance of such modules in various LHCb-RICH configurations. We performed...
PET scanners are indispensable imaging tools in modern medicine. In recent years it was shown that a planar configuration, in contrast to the classical cylindrical shape, could become a practical option, while capable to operate in challenging environments and protocols, such as surgery suit, ER, upright imaging, that are not possible using current PET scanners. For such an open tomograph...
HEPS-BPIX4 is a dual-threshold hybrid pixel detector with 140μm×140μm pixel size and frame rate up to 1.2kHz . The 6M pixel detector is design for HEPS.
The silicon sensors used for the modules were designed at IHEP.The sensors with a thickness of 450um are fully depleted at about 60 V and normally biased with 100 V.
The 6M pixel array detector consists of 40 modules, with a total pixel...
We report on results of irradiation experiments with ring modulators and Mach-Zehnder modulators of our current silicon photonic transmitter chip COTTONTAIL. Ex-situ experiments on ring modulators show a significant degradation from a total ionizing dose of more than 3 MGy and a difference in low and high frequency behavior. Forward bias annealing can mostly restore the pre-irradiation...
For a proposed upgrade of the Belle II experiment an R&D program has been established to develop a new vertex detector (VTX) made from a single type of depleted active monolithic pixel detector named OBELIX. The chip will provide two LVDS data links with a transmission speed of about 339 MHz. To read out the OBLEIX data it is foreseen to utilize optical links based on the lpGBT chip and the...
This poster presents an advanced real-time Wiener deconvolution algorithm designed to take advantage of the FPGAs integrated into the JUNO experiment readout boards. Exploiting online reconstruction of the signal generated by PMTs, we expect to enable the detection of low energy depositions, like those generated by transient astrophysical phenomena.
The features of the algorithm are...
The first processing stage of the HGCAL Backend trigger primitive generator system for the Phase-2 upgrade of the CMS detector will be implemented using the Serenity ATCA platform. This processing stage is responsible for receiving and pre-processing the trigger data coming from the HGCAL front-end and is composed of several firmware blocks. This contribution will present an overview of the...
The ATLAS Strip Tracker for the HL-LHC uses the End-of-Substructure (EoS) card to connect up to 28 data lines from the silicon sensor modules to the lpGBTs and VL+ ASICs. The EoS provides a 10 Gbit/s optical link to the off-detector systems. We report on the production experience with detailed QC statistics, the issues that were identified with the LpGBTv1 and required a complete reproduction....
This study presents optimizations to the Massive Temperature Readout System (MTRS), a low-cost alternative to traditional PLC-based systems for large-scale temperature monitoring. Our improved MTRS design streamlines hardware by eliminating intermediate microcontrollers and communication modules, reducing complexity and potential failure points. A unified multi-threaded C++ application...
The CBM experiment at FAIR will operate with high-rate, slowly extracted beams from SIS100, reaching interaction rates up to 10 MHz in quasi-continuous spills. To support this, a free-streaming data acquisition architecture is employed. Spill fluctuations under high data load can lead to event fragmentation and data loss. A statistical model of the data flow, incorporating data response of...
The data acquisition electronics for the new HL-LHC Beam Position Monitor system will be based on a RFSoC, a System-on-Chip with integrated high-speed Analog-to-Digital Converters and Digital-to-Analog Converters.
While modular systems based on industrial computers and FPGA modules are well known and supported across CERN’s accelerators, SoC based systems are still novel, bringing new...
The iFTDC is a low cost, simple and flexible front-end card designed to measure signal timing for different types of detectors with a precision of 150 ps. It's based on ARTIX-7 FPGA, has 64 LVDS inputs and few user IO pins for configuration of attached ASICs. The FPGA's built-in high-speed serial link connects the board to the DAQ using the Unified Communication Framework protocol. The iFTDC...
For the Phase-2 Upgrade of the CMS Level-1 Trigger, a dedicated ATCA Rear Transition Module for the Serenity ATCA blade has been designed. It is intended to be used by the Phase-2 Global Trigger as well as the Beam Radiation Instrumentation and Luminousity group during operations of the CMS detector. It acts as a generic port expander for the Serenity card and is responsible for signal...
We introduce the FLASH experiment and present its electronic read-out system, currently under development. FLASH uses a resonant-cavity in a magnetic field to search for Dark Matter (DM) particles and High-Frequency Gravitational Waves (HFGWs). The cavity is operated at cryogenic temperatures to improve its performance, uses Superconducting Quantum Interference Devices (SQUIDs) as first-stage...
The Back-End Card (BEC) is a crucial component in the trigger readout chain of the JUNO experiment, serving as the interface between approximately 7,000 Global Control Units (GCUs) and the central trigger system. A total of 163 BECs were installed for deployment in the experiment's underground environment. To support the system's expected long-term operation, we perform a reliability...
To sustain the unprecedented radiation and rates of HL-LHC, the readout and trigger electronics for the Drift Tubes (DT) in CMS have been upgraded. The time digitization is implemented on the new OBDT board, and the data are streamed to the new back-end electronics where event building and trigger primitive generation are performed. The development of a new hardware, called MONitor for SAfety...
The ICARUS Liquid Argon (LAr) Time Projection Chamber (TPC) detector is taking data on the Booster (BNB) and Main Injector (NuMI) neutrino beam lines at Fermilab with a trigger system based on the scintillation light (detected by PhotoMultiplier Tubes PMT) produced by charged particles on the time of proton beam extraction from the accelerators. The layout consists of National Instruments...
Future Terascale-era experiments require scalable, high-performance data acquisition (DAQ) systems to handle extreme data rates. We present a DAQ solution based on the Advanced Mezzanine Card (AMC) standard, under development for the Micro-Vertex Detector (MVD) readout chain of the PANDA experiment. This contribution emphasizes the system’s modularity and scalability. A preliminary test card,...
We present the design, implementation, and characterization of an 8$\times$8 SiPM (AFBR-S4N66P024M) array adapted to the readout electronics of the CBM Ring Imaging Cherenkov detector. The front-end of the array consists of a preamplification stage with low power consumption (12\,mW/channel), high linearity, and low cost. In addition, we evaluated the performance of the SiPMs after neutron...
For the upcoming high-luminosity LHC, the endcap calorimeters of the CMS experiment will be replaced by the high-granularity calorimeter (HGCAL), a sampling calorimeter using silicon sensors in the front and plastic scintillators read out by SiPMs in the back. After successfully integrating the SiPM-on-Tile sensors with the Serenity back-end hardware, we have conducted detailed system tests to...
