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Description
A 12-layered RPC detector stack is operational at TIFR, Mumbai. A cosmic muon veto detector (CMVD) is being developed around this setup as part of a feasibility study for a shallow-depth neutrino detector. It uses extruded plastic scintillator (EPS) strips as the active medium. Muon interactions in the scintillator are detected by silicon photomultipliers (SiPMs) coupled to two wavelength-shifting fibres embedded in each strip.
The detector is designed to achieve a muon detection efficiency exceeding 99.99%. Precise muon identification requires accurate measurement of the SiPM charge. The analogue signals from the SiPMs are converted into voltage pulses using trans-impedance amplifiers and sampled by a DRS4 chip operating at 1 GS/s. The sampled signals are digitised using a fast ADC. Data acquisition is triggered by a cosmic muon signal from the RPC stack, after which zero-suppressed data are transmitted to a back-end server for further waveform analysis and charge extraction.
The data acquisition system is implemented on an AMD Spartan-7 FPGA, which hosts a MicroBlaze soft-core processor for control and process management. The FPGA-based DAQ board under development integrates multiple DRS4 ASICs along with a network interface. This paper presents the development and commissioning of the CMVD DAQ system.
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