Speakers
Description
In our experimental setup for testing calorimeter prototypes at the SPS, digitisation occurs in several ways. The most relevant to trigger system performance is charge measurement with current-integrating analog-to-digital converters (QDCs) in trigger-driven gates.
The main challenge here is the requirement that the current-integrating gate precede the QDC analog signals by at least 15 ns. Added to this is the trigger formation latency, which, with modular NIM electronics, approaches 50 ns. With FPGAs, we could only achieve marginal improvements, meaning we would have to compensate for 60-70 ns of total latency in signal arrival time.
For these reasons, we decided to design a low-latency asynchronous trigger board from scratch with discrete negative ECL electronics, targeting a total latency close to 15 ns.
Due to NECL limited chip portfolio, we identified the MAX9600 dual comparator and the MC10EL31 D flip-flop (configured as one-shot) as the logic building blocks.
The initial implementation (on a 2-layer PCB homemade due to time constraints) suffers from crosstalk and noise (we had to add decoupling capacitors and shielding in many places) and, to a much lesser extent, from the fact that the pulse duration is defined by an RC feedback loop.
Nonetheless, the board proved crucial (with excellent performance) for the beam tests we conducted in autumn 2025.
Methods for tagging problematic events were identified and implemented in the DAQ system and the total latency was estimated at about 13 ns.
Possible improvements under investigation include moving to a 4-layer PCB, for improved immunity to noise and crosstalk, digital control of the comparator thresholds, and the use of software-controllable delay lines for setting the one-shot pulse duration.