17–21 Sept 2012
Oxford University, UK
Europe/Zurich timezone

Development and Implementation of Optimal Filtering in a Virtex FPGA for the Upgrade of the ATLAS LAr Calorimeter Readout

18 Sept 2012, 15:40
25m
Lindemann Lecture Theatre (Oxford University, UK)

Lindemann Lecture Theatre

Oxford University, UK

<font face="Verdana" size="2"><b>Clarendon Laboratory</b> Parks Road OX1 3PU, Oxford, United Kingdom
Oral B2

Speaker

Steffen Staerz (TU Dresden)

Description

In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation at the High-Luminosity LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming trigger signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

Summary

The current read-out system of the ATLAS Liquid-Argon (LAr) Calorimeters provides signals sampled at 5 time steps, which are sent by the Front-End Boards on a positive trigger decision at a 75 kHz mean rate. The receiving back-end electronics calculates energy, time and pulse quality factor for each detector cell using a FIR filter to suppress electronics and pile-up noise. The resulting data are eventually transmitted to the high-level trigger and data acquisition systems. In the upgrade model developed to cope with the conditions of the High-Luminosity LHC (HL-LHC), an additional data stream with high-granularity trigger information is planned to be sent to a new Digital Processing System (DPS) on every bunch crossing at a rate of 40 MHz. After signal processing, the data are passed to a new trigger component which identifies physics objects.
Eventually, the trigger information is merged with the current trigger system, which performs the final trigger decision. The basic task of the DPS is to calculate the energy deposits from incoming pulses for each trigger super-cell, very similar to the current back-end system. However, additional aspects need to be taken into account: a continuous incoming data stream, a more strict latency, a signal filtering adjustable to increased and varying pile-up noise conditions, and the ability to identify “interesting” energy deposits and identify the corresponding LHC bunch-crossing in the data stream. In order to evaluate the quality of different DPS filter algorithms, three main criteria were selected with weights between 0 and 1: the relative accuracy of the energy output of the filter, the number of physics signals not recognized by the filter, and the number of faked physics signals. The overall quality is defined as the product of these weights and is evaluated as a function of the physics signal amplitude.
The performance of different filter algorithms is simulated for varying signal and pile-up rate including electronic noise. In particular the energy reconstruction in a trigger super-cell, built of 4 individual LAr channels, is analyzed. From the variety of known filter algorithms, adaptive filters were investigated first but discarded because of the adjustment sequence. The current FIR filter, an IIR filter, an inverse FIR filter, a Wiener filter and a Heuristic filter were found more promising and thus investigated further. None of them were applicable directly to the pile-up scenario expected for the LAr Calorimeters at HL-LHC, and needed modifications to meet requirements. From simulation, the Heuristic and the Wiener filter were identified as performing best. A derivative-based filter with little FPGA resource utilization was also implemented for comparison.

The talk will present different filter algorithms and their simulated performance results for the read-out of the trigger super-cells of the LAr Calorimeter. In the second part, details of the implementation of the filters in a Virtex FPGA, their resource utilization, multiplexing capability and final throughput are shown and compared with respect to the target application.

Author

Steffen Staerz (TU Dresden)

Presentation materials