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Description
Summary
The ATLAS Tile Calorimeter phase 2 upgrade demonstrator aims at installing a hybrid on-detector electronic system replacing 1-4 adjacent drawers in the ATLAS detector starting at the end of the first long shut-down period. While being a fully functional prototype of the future on-detector electronics it will also be made compatible with the present system. In the new system the current motherboard, digitizer, mezzanine and interface card will be merged into a two board solution, a MainBoard for data acquisition and a link DaughterBoard for off-detector communication. To reach this goal several tasks have to be performed. We have already created a rough model of the readout hardware using mostly off the shelf components for firmware development and started the hardware development process resulting in an early prototype of each of the two boards. After evaluating all test results we are now redesigning the link DaughterBoard prototype. This time we have used one of the latest technology FPGAs, redesigned the connector to the data acquisition board and increased the high speed communication capability.
The new FPGA is a XILINX Kintex7 manufactured with reduced power consumption as well as increased maximum transmission speed for serial data communication. In comparison to the previously used XILINX Virtex6 this FPGA consumes about 40% less power and is able to transmit data with up to 10.3Gbps line speed. As communication interface the previously used two SFP+ connectors were replaced by one QSFP+ connector running with 10Gbps. This connector should be used in parallel with the current SNAP12 connector to study pros and cons. The final decision about which link to use will be made by the TileCal community.
To improve clocking capability one CDCE62005 per side was added. In the final revision this IC should be replaced by a GBTX connected to the QSFP+, to extract the LHC clock along with data used for reprogramming of the FPGA.
The in system programmability (ISP) will make use of a special feature allowing reprogramming the FPGA from a connected radiation hard flash memory which can be rewritten using the GBTX chip when available. In this version programming the memory and FPGA is realized using a separate parallel user interface emulating the GBTX.
