Speaker
Jacobus Willem Van Hoorne
(Vienna University of Technology (AT))
Description
As a major part of its upgrade plans, the ALICE experiment schedules the installation of a novel Inner Tracking System (ITS) during the Long Shutdown 2 of the LHC in 2018/19. It will replace the present silicon tracker with 7 layers of Monolithic Silicon Active Pixel Sensors (MAPS) and significantly improve the detector performance in terms of tracking and rate capabilities. The choice of technology has been guided by the tight requirements on the material budget of 0.3 X$_{0}$ for the three innermost layers and backed by the significant progress in the field of MAPS in recent years.
The new ITS will in total cover a surface of 10.3 m$^2$ with approximately 25 $\times$ 10$^9$ pixels. The pixel chips are manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with high resistivity epitaxial layer. Within the ongoing R&D phase, several sensor chip prototypes have been developed and produced on different epitaxial layer thicknesses and resistivities. These chips are being characterised for their performances before and after irradiation using source tests, test beam and measurements using an infrared laser.
The present contribution will provide an overview of the ALICE ITS upgrade with a focus on the R&D activities on the pixel chip.
Primary author
Jacobus Willem Van Hoorne
(Vienna University of Technology (AT))
