Speaker
Dr
Peter Elmer
(Princeton University (US))
Description
In the last decade power limitations led to the introduction of
multicore CPU's. The cores on the processors were however not
dramatically different from the processors just before the
multicore-era. In some sense, this was merely a tactical choice to
maximize compatibility and buy time. The same scaling problems that
led to the power limit are likely to push processors in the direction
of ever greater numbers of simpler, less performant lower-power
cores. Without this architectural change, it is doubtful if the
gains expected from a Moore's Law extrapolation will continue to
be realized over the next five years.
Although it is very hard to predict where the market will wind up
in the long run, we already see today a couple of concrete product
examples which give indications as to the kinds of things that we
will see going forward, namely Intel's Many Integrated Core (MIC)
architecture and the ARM processor. The first MIC commercial products
(Xeon Phi) are in the form of a coprocessor and aimed at the HPC
market. 32bit ARM is ubiquitous today in mobile electronics and the
64bit version (ARMv8) is expected to make a debut in the server
space this year.
In this presentation we report on our first investigations into the
viability of the ARM processor and Intel Xeon Phi processors. We
use benchmarks with real physics applications and performance
profiles to explore the viability of these processors for production
physics processing. We investigate what changes would be necessary
for complete, large applications to perform efficiently and in a
scalable way on these kind of processors.
Primary authors
David Abdurachmanov
(Vilnius University (LT))
Gene Cooperman
(Unknown)
Mr
Giulio Eulisse
(Fermi National Accelerator Lab. (US))
Mr
Kapil Arya
(Northeastern University)
Dr
Peter Elmer
(Princeton University (US))
Shahzad Malik Muzaffar
(Fermi National Accelerator Lab. (US))
