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Description
Summary
A 32 channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and submitted for fabrication in a 130 nm CMOS technology.
This chip is the successor of a High Performance TDC (HPTDC), which has been implemented in a commercial 250 nm technology achieving a resolution of 100 ps based on a Delay Locked Loop (DLL). The HPTDC is used in a variety of applications, with the largest one in terms of number of channels being the time of flight detector in the ALICE experiment at CERN. An RC delay line performs an additional interpolation in order to reach the required resolution of 25 ps at the cost of reducing the number of channels to 8, instead of 32. Contrary to a DLL, which is self-calibrating, RC delay lines need offline calibration. To implement 160 000 channels with 25 ps bin size, 20 000 HPTDCs are necessary, while the new development (TDC130) would require only 5 000 parts.
In the TDC130, an on-chip Phase Locked Loop (PLL) is used to generate an internal timing reference with a period of 780 ps from an external 40 MHz clock source. In order to further increase the resolution, a 32 element DLL performs the time interpolation. The prototype contains a PLL, a DLL, registers for event timestamps of the 32 channels and a band-gap voltage reference for biasing circuits. All channels share one common DLL time base in order to minimize the power consumption. The measurement is relative to the 40 MHz external clock and the bin size is a binary fraction of a 25 ns period, simplifying the encoding of the measurement. Furthermore, a programmable noise generator with an independent clock source is included in order to evaluate the sensitivity of the circuit to substrate and power supply noise. As the TDC130 is targeted at high energy physics (HEP) applications, it supports a high rate of measurements (3 MHz per channel). The maximum hit rate on one channel does not depend on the activity on other channels, as, contrary to the HPTDC, the level 1 buffers are not shared amongst multiple channels.
In order to reduce the bandwidth required for readout, a mechanism to store all measurements, but to read out only those that are considered interesting and signalled by a trigger signal, is implemented. This technique is frequently used in HEP applications. In other applications, a trigger system might not be available and thus all data needs to be extracted, a mode of operation also supported by the TDC130. The architecture is thus suitable both for triggered and non-triggered applications.
The paper describes the circuit architecture and its principles of operation. Depending on the fabrication schedule measurement results might be available at the time of the conference.
