TWEPP-08 Topical Workshop on Electronics for Particle Physics

Europe/Athens
Naxos - GREECE

Naxos - GREECE

Francois Vasey (CERN)
Description

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

It is continuing and expanding the scope of the former workshop on electronics for LHC and future experiments (LECC), LHC experiments will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purposes of the workshop are :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

The deadline for abstract submission has been extended to 18 May 2008

Further information and news on the workshop will be provided at http://www.ntua.gr/twepp08

Support
    • Plenary Session 1 - OPENING
      • 1
        Welcome 1
        Speaker: Francois Vasey (CERN)
        Slides
      • 2
        Welcome 2
        Speaker: Manolis Dris (Physics Department)
      • 3
        An overview of the Experimental High Energy Activity in Greece
        On behalf of the Greek HEP Community The major contributions of the Greek Experimental High Energy Community in both Accelerator and non-Accelerator experiments in the last decade will be presented. The strong points of the HEP scientific community will be stressed and an outlook for the future activities will be outlined with emphasis on carrying joint R&D projects and participating in future High Energy Physics Experiments.
        Speaker: Ms Chariclia Petridou (Atomic and Nuclear Physics Laboratory)
        Slides
      • 4
        Greek Contribution to the ATLAS experiment
        The Greek contribution to the construction and commissioning of the ATLAS Muon spectrometer will be reviewed. In addition, the physics studies, leading to lepton final states, performed by the Greek Groups will be summarized.
        Speaker: Mrs Christine Kourkoumelis (University of Athens)
        Paper
        Slides
      • 5
        CMS in Greece
        In this report the contribution of the Greek teams participating in CMS experiment is briefly presented. The contribution refers to the CMS Preshower, the CMS trigger/DAQ system, the CASTOR forward calorimeter, the CMS physics reconstruction and selection, and the preparation for Physics analysis
        Speaker: Dr Nikolaos Manthos (University of Ioannina, Physics Department)
        Slides
    • 15:35
      Break
    • Plenary Session 2 - OPENING
      • 6
        NESTOR participation in the KM3NeT
        NESTOR Collaboration is a key player in the Design Study of the KM3NeT, the European Deep Sea Neutrino Telescope and claims to have the best site in the Mediterranean for this. In this report we describe briefly the site properties, the pioneer NESTOR expertise, our contribution towards the KM3NeT and present the specially constructed, for telescope modules deployments, ship-platform "DELTA-BERENIKE".
        Speaker: Efstratios Anassontzis (University of Athens - Physics Department - Nuclear and Particle Physics Section)
        Paper
      • 7
        The European XFEL Project
        The European XFEL project is a 4th generation photon source to be built in Hamburg. Electron bunches, accelerated to 17.5GeV by the XFEL linac, are distributed to three SASE long undulators. There photon pulses with full lateral coherence and wavelengths between 0.1nm and 4.9nm (12.4keV and 0.8keV) are generated for three beamlines. It will deliver around 1012 photons within each 100fs pulse, reaching a peak brilliance of 1033 photons s 1mm 2 mrad 2 (0.1%BW)-1. Thus it will offer unprecedented possibilities in photon science research including nano-object imaging and studies (e.g. by coherent X-ray scattering) and ultra fast dynamic analysis of plasma and chemical reactions (e.g. by X-ray photo correlation spectroscopy). The detector requirements for such studies are extremely challenging: position sensitive area detectors have to provide a dynamic range of ≥104, with single-photon sensitivity, while withstanding radiation doses up to 1GGy (TID). Furthermore the detectors have to record data from “trains” of up to 3000 photon pulses, delivered at 5MHz, which repeat every 100ms. Three consortia have picked up the challenge to build pixel detectors for the European XFEL: DepFet, HPAD and LPD. Besides the European XFEL source and the related experimental techniques, the concepts and specialities of the DepFet, HPAD and LPD detectors are discussed
        Speaker: Dr Ulrich Trunk (DESY)
        Paper
        Slides
      • 8
        Development of a 3.2 GPixel Camera for the Large Synoptic Survey Telescope (LSST)
        The LSST is an 8.4 meter survey telescope currently under development for operation on the 2,700 meter Cerro Pachon mountaintop in central Chile. LSST will have features which make it uniquely capable of carrying out multiple science missions including “Type 1A” supernovae surveys to constrain dark energy parameters, weak lensing probes for dark matter tomography, transient phenomena, galactic structure, and “Near Earth Asteroid” (NEA) discovery. These science goals impose strict requirements and challenges for the LSST camera. These include a wide-field (3.2 GPixel), high quantum efficiency focal plane, and 3,200 channels of high speed, low noise readout electronics contained within the camera. This paper describes those challenges and the development of the camera, its sensors, and the readout electronics required to meet them.
        Speaker: Mr John OLIVER (Havard University)
        Slides
    • 18:30
      Welcome Drink
    • 9
      Executive Summary
      Paper
    • Plenary Session 3 - FPGAs in 2008 and Beyond
      • 10
        FPGAs in 2008 and Beyond
        Since 90 nm, Moore’s Law offers diminishing performance increase, requires architectural changes: Bigger LUTs, dedicated hard cores, microprocessors and transceivers. Virtex-5 had excellent start in 2007 In 2008: Virtex-5 FXT. PPC440 with attached 5 x 2 Crossbar for performance and flexibility. GTX Transceivers achieve 6.5 Gbps data throughput. After 2008 through 2013: 45 nm followed by 32 nm technology. More transistors and lower cost per function. (average 10% per year, or factor 10 every 7 years)) Capacity limited by die size Performance limited by power and heat budget. Various effects and trade-offs are discussed.
        Speaker: Prof. Volker Lindenstruth (KIP Uni-Heidelberg)
        Slides
    • Parallel session A1 - ASICs
      • 11
        New sensors for particle detection with in-situ charge storage
        Image Sensors with In-situ Storage (ISIS) are being developed for use in future linear collider and fast imaging applications. The ISIS device consists of pixels each with a short charge storage register. Charge is collected by a photogate and stored in one of many in-pixel storage registers, for readout during quiet periods in the beam duty cycle. For an ILC application it is expected that 20 storage cells and a relatively low readout rate of 1MHz will be sufficient. I will present the results in testbeam of a CCD-based proof of principle device, with 16 x 16 ISIS cells with a buried channel CCD storage register in each. A new device is currently being fabricated in a CMOS 0.18 micron process, and is due out at the time of the workshop. It incorporates interesting features of CCD-like buried channel and deep p+ shielding implants, which allow efficient charge collection and integration of readout structures on the same wafer.
        Speaker: Dr Steve Worm (Rutherford Appleton Laboratory)
        Slides
      • 12
        A MAPS-based readout for Tera-Pixel electromagnetic calorimeter at the ILC
        The leading proposed technology for electromagnetic calorimeters for ILC detectors is a highly granular silicon-tungsten calorimeter. We have developed an active pixel sensor for such a calorimeter, which would have extremely fine granularity, allowing binary pixel readout. A first generation chip (TPAC1) has been fabricated, and this contains a 168x168 pixel array, consisting of 50x50 micron pixels. Each pixel has an integrated charge pre-amplifier and comparator. TPAC1 has been manufactured in the 0.18 micron CMOS INMAPS process which includes a deep p-well. We present recent results of the performance of the TPAC1 chip together with comparison to device-level simulations.
        Speaker: Jamie Crooks (Rutherford Appleton Laboratory)
        Paper
        Slides
    • Parallel session B1 - Trigger 1
      • 13
        The Level 0 Pixel Trigger System for the ALICE Silicon Pixel Detector: implementation, testing and commissioning.
        The ALICE Silicon Pixel Detector transmits 1200 Fast-OR signals every 100 ns using its 120 optical readout channels. They indicate the presence of at least one hit in the pixel matrix of each readout chip. The ALICE Level 0 Pixel Trigger system extracts, processes them and delivers an input signal to the Central Trigger processor for the first level trigger decision within a latency of 800 ns. This contribution will describe the tests and measurements made during the qualification and commissioning phases of the system. These included Bit Error Rate tests on the Fast-OR data path, the measurement of the overall process latency and the recording of calibration data with cosmic rays. Furthermore, the first results of the operation of the Pixel Trigger system with the SPD detector in the ALICE experiment will be presented.
        Speaker: Dr Gianluca Aglieri Rinella (CERN)
        Paper
        Slides
    • 10:35
      Break
    • Parallel session A1 - ASICs
      • 14
        Development of FE-I4 pixel readout IC
        A new hybrid pixel readout integrated circuit denominated FE-I4 is being developed for use in ATLAS upgrades. The design goals include 4 times higher rate capability, 4 times the active area (full reticule), and 38% smaller pixels than the presently used FE-I3 IC. The target applications are a possible smaller radius replacement of the present inner layer and/or outer layers or disks of a super-LHC detector. For the innermost layer of a super-LHC detector a further design generation will be needed, and the present effort serves as a stepping stone towards this ultimate goal. Small size analog/digital prototype blocks have been fabricated in 0.13um feature size bulk CMOS technology. An overview of the full chip design-in-progress is presented, along with status and test results from various test chip prototypes.
        Speaker: Mr Michael Karagounis (Bonn Physics University)
        Paper
        Slides
      • 15
        Development of a Front-end Pixel Chip for Read-out of Micro-Pattern Gas Detectors.
        With a growing need for high resolution, radiation hard and low mass pixel detectors the Micro-Pattern Gas Detector is a good candidate. This detector requires a dedicated front-end read-out chip with improved readout architecture to deal with the high data rate. In addition, it is highly required to keep power consumption as low as possible. Some of prototype IC’s have already been submitted and tested in order to demonstrate high performance of a new front-end (preamplifier and comparator) and feasibility to implement high resolution TDC-per-pixel architecture. In line with the present results we will discuss design goals and system requirements for a full-reticle chip.
        Speaker: Vladimir Gromov (NIKHEF)
        Paper
        Slides
      • 16
        Design and Characterisation of a Fast Architecture Providing Zero Suppressed Digital Output Integrated in a High Resolution CMOS Pixel Sensor for the STAR Vertex Detector and the EUDET Beam Telescope
        CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, requiring sensors featuring digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. An architecture will be presented, combining a pixel array, column-level discriminators and zero suppression circuits. Each pixel features a preamplifier and a signal processing circuit (CDS) reducing the temporal and fixed pattern noise. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.
        Speaker: Ms Christine HU-GUO (DRS-IPHC Strasbourg (IReS))
        Paper
        Slides
      • 17
        A Pixel Read-Out Architecture for the NA62 Gigatracker with on Pixel Time-To-Digital Conversion and Data Derandomization.
        The NA62 experiment will need hybrid pixel sensors with a size of 300 um x 300 um and a time resolution of 150 ps (rms). To meet the timing requirement an adequate strategy to compensate the discriminator time-walk must be implemented and an R&D effort investigating two different options is ongoing. In this presentation we describe the two different approaches. One is based on the use of a costant-fraction discriminator followed by an on-pixel TDC. The other one is based on the use of a Time-over-Threshold circuit followed by a TDC shared by a group of pixels. The global architectures of both the front-end ASIC will be discussed
        Speaker: Giulio Dellacasa (Istituto Nazionale di Fisica Nucleare (INFN))
        Paper
        Slides
      • 18
        A Pixel readout architecture for the NA62 Gigatracker based on End Of Column TDC
        We present the ASIC development of the readout electronics of the Gigatracker pixel detector of NA62. Gigatracker speed , noise and power performance are very challenging and 2 architectures , are in phase of R&D demonstration to further select the best approach. Circuits configuration of the constant fraction discriminator with on pixel TDC and of the time-over-threshold discriminator with end-of-column DLL based TDC are presented and discussed. Spice simulations and layouts of the demonstrator circuits developed in 130 nm CMOS technology are presented and discussed.
        Speaker: Pierre Jarron (CERN)
        Paper
        Slides
    • Parallel session B1 - Trigger 1
      • 19
        First results on the performance of the CMS Global Calorimeter Trigger
        The CMS Global Calorimeter Trigger (GCT) has been designed, manufactured and commissioned on a short time schedule of approximately two years. The GCT system has gone through extensive testing on the bench and in-situ and its performance is well understood. This paper describes problems encountered during the project, the solutions to them and possible lessons for future designs, particularly for high speed serial links. The input links have been upgraded from 1.6Gb/s synchronous links to 2.0Gb/s asynchronous links. The existing output links to the Global Trigger (GT) are being replaced. The design for a low latency, high speed serial interface between the GCT and GT, based upon a Xilinx Virtex 5 FPGA is presented.
        Speaker: Dr Gregory Michiel Iles (Imperial College)
        Paper
        Slides
      • 20
        Operation and Monitoring of the CMS Regional Calorimeter Trigger
        The electronics for the Regional Calorimeter Trigger (RCT) of the Compact Muon Solenoid Experiment (CMS) have been produced, tested, and installed. The RCT hardware consists of 1 clock distribution crate and 18 double-sided crates containing custom boards, ASICs, and backplanes. The RCT receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the CMS Global Calorimeter Trigger (GCT) after processing. Integration tests with the TPG and GCT subsystems have been successful. Installation is complete and the RCT is integrated into the Level-1 Trigger chain. Data-taking, triggered with cosmic ray muons, is now regular. Progressively, the operation and configuration of the RCT has moved from mostly hands-on to a completely automated process. The tools to monitor, operate, and debug the RCT are mature and will be described in detail, as well as the results from cosmic muon data-taking with the RCT.
        Speaker: Mrs Pamela Klabbers (University of Wisconsin)
        Paper
        Slides
      • 21
        Analysis of the initial performance of the ATLAS Level-1 Calorimeter Trigger
        The ATLAS first-level calorimeter trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates and to measure total and missing ET in the calorimeters. The installation of the full system of custom modules, crates and cables was completed in late 2007, but, even before the completion, it was being used as a trigger during ATLAS commissioning and integration. During 2008, the performance of the full system has been tuned during further commissioning and cosmic runs, leading to its use in initial LHC data taking. Results and analysis of the trigger performance in these runs will be presented.
        Speaker: Dr Damien Prieur (STFC, Rutherford Appleton Laboratory)
        Paper
        Slides
      • 22
        Digital signal integrity and stability in the ATLAS Level-1 Calorimeter Trigger
        The ATLAS first-level calorimeter trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates and to measure total and missing ET in the ATLAS calorimeters. Apart from the initial analogue stage, the trigger system consists of a multi-stage pipelined digital processor distributed over several crates of custom-built modules. The high demands for interconnectivity between both crates and modules are solved by a variety of high-speed digital links, using several signaling standards, including both electrical and optical transmission. The techniques used to establish timing regimes, and verify correct connectivity and stable operation of these digital links, will be presented.
        Speaker: Ms Andrea Neusiedl (University of Mainz)
        Paper
        Slides
    • 13:05
      Lunch
    • Plenary Session 4 - Optoelectronics, a global telecom carrier's perspective
      paper
      slides
      • 23
        Optoelectronics, a global telecom carrier's perspective
        This paper summarises the current approaches to high speed optical transmission design. Cable&Wireless operates a large global optical transmission network, with the main purpose of serving the bandwidth market and of providing connectivity for its Internet Protocol data networks. In long haul spans, dense wavelength division multiplexed systems with aggregate capacities of 1Tbit/s per fibre are deployed. The increase in bandwidth requirement is driving the need for more complex technologies that deliver a jump in system capacity. Emerging optoelectronic technologies are discussed, with particular focus on 40 Gbit/s per wavelength transmission and optical wavelength switching.
        Speaker: Dr Jeremy Batten (Cable&Wireless)
        Paper
        Slides
    • Parallel session A2 - ASICs
      • 24
        SPIROC (SiPM Integrated Read-Out Chip): Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out
        SPIROC embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 1 ns accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4kbytes RAM.
        Speaker: Mr Julien Fleury (Laboratoire de l'Accélérateur Linéaire)
        Paper
        Slides
      • 25
        A Readout ASIC for CZT and Si Detectors
        Spectrometers that can identify the energy of gamma radiation and determine the source isotope have until recently used low temperature semiconductors. These require cooling which makes their portability difficult. A relatively new material, cadmium zinc telluride, is now available which operates at room temperature and can be used to measure the energy of gamma radiation. In a compton camera configuration the direction of the radiation can also be determined. A read-out ASIC has been developed which detects the ionised charge in such a system and processes this before outputting to a data acquisition system. ASIC test results will be presented.
        Speaker: Mr Lawrence Jones (STFC)
        Paper
        Slides
    • Parallel session B2 - Optoelectronics
      • 26
        Evaluation of Multi-Gbps Optical Transceivers for Use in Future HEP Experiments
        Future experiments at CERN will increase the demand for high-bandwidth optical links. Custom developments for deployment within the detector volumes will be based upon commercially available transceivers. We present our evaluation of commercial multi-Gbps optical transceivers and optoelectronic components. This serves as the basis to evaluate the performance of the future Versatile Transceiver that is being developed at CERN in the context of the Versatile Link project. We describe the experimental set-up for parametric testing, the devices evaluated and our treatment of the performance data.
        Speaker: Dr Luis Amaral (CERN)
      • 27
        Experiences with the ATLAS Pixel Detector Optolink and researches for future links
        The ATLAS Pixel optical link connects the readout electronic in the counting room and the active detector elements. After installation the link has been comissioned and tuned. Tests for optical and electrical functionality of components sorted out failures on the off-detector side and had the system more than 99% functional after installation. For optical links in future detectors in higher radiation environments thermal effects in laser-diodes become essential and have to be understood. A research program to study thermal properties and its consequences will be discussed and is performed in the context of the Joined ATLAS/CMS activities.
        Speaker: Mr Jens Dopke (University of Wuppertal)
        Paper
        Slides
    • 15:50
      Break
    • Parallel session A2 - ASICs
      • 28
        Status Report on the LOC ASIC
        The LOC ASIC is a serializer for data transmission. This ASIC development is supported by US-ATLAS upgrade program, and is based on a 0.25 μm Silicon on Sapphire technology. Characterization tests on the technology and the first prototype LOC1 have been carried out both in lab and in irradiation tests. Measurement results on jitter and Bit Error Rate of the ASIC as well as the TID and SEE effects will be reported. Design considerations, specifications and simulation results on the second prototype LOC2 will be discussed
        Speaker: Prof. Jingbo Ye (Southern Methodist Univeristy, Dpt of Physics)
        Paper
        Slides
      • 29
        Evaluation of Two SiGe HBT Technologies for the ATLAS sLHC Upgrade
        As previously reported, silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies promise several advantages over CMOS for the ATLAS upgrade [8]. Since our last paper, we have evaluated the relative merits of the latest generations of SiGe HBT BiCMOS technologies, the 8WL and 8HP platforms. These 130nm SiGe technologies show promise to operate at lower power than CMOS technologies and would provide a viable alternative for the Silicon Strip Detector and Liquid Argon Calorimeter upgrades, provided that the radiation tolerance studies at multiple gamma, neutron, and proton irradiation levels included in this investigation show them to be sufficiently radiation tolerant.
        Speaker: Dr Miguel Ullan (CNM-IMB (CSIC), Barcelona)
        Paper
        Slides
      • 30
        The ABCN front end chip for ATLAS Inner Detector Upgrade
        We present the design of the ABCN front end chip implemented in CMOS 0.25um technology and optimized for short, 2.5cm, silicon strip detectors intended to be used for the upgrade of ATLAS Inner Detector tracker. A primary aim of this project is to develop an ASIC with full functionality as required for readout of short silicon strips in the SLHC environment in a cost-effective and proven technology. Efforts have been put on minimization of the power consumption and compatibility with new power distribution schemes being developed for future tracker detectors. The architecture of the chip as well as critical and novel design aspects will be presented. The ABCN ASIC will serve as a basic testing vehicle in extensive programs on developments of sensor and modules for the upgrade of Inner Detector.
        Speaker: Jan Kaplon (CERN)
        Paper
        Slides
    • Parallel session B2 - Optoelectronics
      • 31
        Study of radiation hardness of PiN diodes for Atlas pixel detector
        The ATLAS has started the upgrade project to address the upgrade of the LHC luminosity by factor of 10. ATLAS pixel tracker employs optical links for communication between the sensors and data acquisition. We study the radiation hardness of PiN diodes which are part of the optical link. These components were irradiated by 200 MeV protons up to 40 MRad and by gamma source up to 10 MRad. The responsivity, dark current of PiN diodes are measured as a function of the radiation dose.
        Speaker: Mr Babak ABI (Oklahoma State University)
        Slides
      • 32
        Single-Event Upsets in Photodiodes for Multi-Gb/s Data Transmission
        A Single-Event Upset study has been carried out on PIN photodiodes from a range of manufacturers. A total of 22 devices of eleven types from six vendors were exposed to a beam of 63MeV protons. The angle of incidence of the proton beam was varied between normal and grazing incidence for three data-rates (1.5, 2.0 and 2.5Gb/s). We report on the cross-sections measured as well as on the detailed statistics of the interactions measured using novel functionalities in a custom-designed Bit Error Rate Tester. Upsets lasting for multiple bit periods have been observed and the fraction of errors when a logical zero is transmitted has been measured to be less than one over a large range of input optical power.
        Speaker: Dr Jan Troska (CERN)
        Paper
        Slides
      • 33
        Design and Radiation Assessment of Optoelectronic Transceiver Circuits for ITER
        We present the design and characterization results of different electronic building blocks for a MGy gamma radiation tolerant optoelectronic transceiver aiming at ITER applications. The circuits are implemented using the 70GHz fT SiGe HBT in a 0.35µm BiCMOS technology. A VCSEL driver circuit has been designed and measured up to a TID of 1.6 MGy and up to a bit rate of 622Mbps. No significant degradation is seen in the eye opening of the output signal. On the receiver side, both a 1GHz, 3kΩ transimpedance and a 5GHz, 20dB Cherry-Hooper amplifier have been designed.
        Speaker: Prof. Paul Leroux (K.H.Kempen)
        Paper
        Slides
    • MICRO ELECTRONICS USER GROUP
      • 34
        Access to ASIC Design Tools and Foundry Services at CERN
        Speaker: Dr Kostas Kloukinas (CERN)
        Slides
      • 35
        Discussion
    • OPTO ELECTRONICS WORKING GROUP: Optoelectronics Working Group
      • 38
        Discussion
      • 39
        Reference Chain
        Speaker: Jingbo Ye (Southern Methodist University, Department of Physics)
        Slides
      • 40
        Discussion
      • 42
        Collaborational Effort on Radiation Tests (report from subgroup B)
        Speaker: Cigdem Issever (University of Oxford)
        Slides
      • 43
        Fibre Irradiation Tests Results of Oxford and SMU
        Speaker: Todd Brian Huffman (Nuclear Physics Laboratory)
        Slides
      • 44
        Radiation Results on PINs
        Speaker: Prof. K.K. Gan (The Ohio State University)
        Slides
      • 45
        Discussion
    • Plenary Session 5 - Commissioning the LHC machine and interlocking with experiments
      slides
      • 46
        Commissioning the LHC Accelerator and its Physics Programme
        The LHC is an accelerator with unprecedented complexity where the energy stored in the magnets and in the beams exceeds that of other accelerators by one-to-two orders of magnitude. An initial phase of so-called "hardware commissioning" has thus been introduced, during which the comprehensive commissioning of all technical systems is undertaken without beam in an effort to ensure a safe and reliable start-up of the LHC accelerator and in order to minimise any technical problems. This paper presents the experience from this approach and presents the results. The strategy for the staged commissioning period with beam that is to follow the "hardware commissioning" phase is also presented. Typical accelerator parameters and associated performance levels are given for each stage with beam and a typical LHC accelerator schedule is shown. All experiments will have installed initial detectors and will be ready for commissioning with beam at the start of LHC operation in 2008. The physics programme is expected to be rich even at the projected initial luminosities. This talk also presents the requirements and expectations of the experiments for the accelerator start-up with beam and early collisions, the heavy-ion runs and the special proton runs, initial conditions that may be used subsequently to set priorities in order to exploit optimally the first LHC beams for physics.
        Speaker: Thijs Wijnands (CERN)
        Slides
      • 47
        3D IC Pixel Electronics, the next challenge
        Articles and advertisements related to 3D integrated circuits are now common in IC trade magazines. Numerous conferences and workshops are dedicated to developing the technologies needed for 3D ICs. Although HEP cannot drive the development of 3D technology, our community should be prepared to take advantage of the advances that are being made. In particular, there are new opportunities for pixel detectors in HEP that exploit the technologies being developed in industry for CMOS image sensors. This talk will present an overview of 3D technology, describe potential advantages for HEP, present results of the first 3D IC for HEP, and describe future plans in HEP to explore this technology. Looking to the future, 3D may be the next big challenge for HEP electronics designers.
        Speaker: Mr Ray Yarema (FERMILAB)
        Paper
        Slides
    • 10:30
      Break
    • Parallel Session A3 - Installation & Commissioning
      • 48
        Mobile Test Bench for the LHC Cryogenic Instrumentation Crate Commissioning
        The installation of the Large Hadron Collider (LHC) at CERN is completed. The magnets are installed and the emphasis is shifted to the commissioning. This work focuses on the commissioning of the cryogenic instrumentation. The LHC is a two-ring superconducting accelerator and pp collider of 27 km circumference.. The dipoles will operate at 8.3 T, cooled by superfluid helium at 1.9 K. The operation and monitoring of the LHC require a massive amount of cryogenic instrumentation channels with a robust and reliable design. The cryogenic control system has to manage about 33000 input-output signals as well as 4000 control loops.
        Speaker: Dr Rachel Avramidou (CERN and National Technical University of Athens)
        Paper
        Slides
      • 49
        The Radiation Tolerant Electronics for the LHC Cryogenic Controls: Basic Design and First Operational Experience
        The LHC optics is based in the extensive use of superconducting magnets covering 23 km inside the tunnel. The associated cryogenic system for keeping the magnets in nominal conditions is hence distributed all around the 27 km LHC tunnel and the cryogenic instrumentation submitted to the LHC radiation environment is composed of close to 18’000 sensors and actuators. Radiation Tolerant (RadTol) electronics was designed and procured in order to keep the signals integrity against electromagnetic interference and to reduce cabling costs required in case of sending the analog signals into the 30 radiation protected areas. This paper presents the basic design, the qualification of the main RadTol components and the first operational results .
        Speaker: Dr Juan Casas-Cubillos (CERN)
        Paper
        Slides
      • 50
        Results from the Commissioning of the ATLAS Pixel Detector
        The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. Approximately 80 M electronic channels of the detector, made of silicon, allow to detect particle tracks and secondary vertices with very high precision. After connection of cooling and services and verification of their operation the ATLAS Pixel Detector is now in the final stage of its commissioning phase. Prior to the first beams expected in Summer 2008, a full characterization of the detector is performed. Calibrations of optical connections, verification of the analog performance and special DAQ runs for noise studies are ongoing. Combined operation with other subdetectors in ATLAS will allow to qualify the detector with physics data from cosmic muons and colliding beam interactions. The talk will show all aspects of detector opration, including the monitoring and safety system, the DAQ system and calibration procedures. The summary of calibration tests on the whole detector as well as analysis of physics runs will be presented.
        Speaker: Lucia Masetti (Institut fur Physik)
        Paper
        Slides
      • 51
        Design, production and first operation of the ALICE Silicon Pixel Detector system
        The ALICE Silicon Pixel Detector (SPD) constitutes the two innermost barrel layers of the ALICE experiment. The SPD is the detector closest to the interaction point, mounted around the beam pipe at r=3.9 cm and 7.6 cm, respectively. In order to reduce multiple scattering the material budget per layer in the active region has been limited to ≈1% X0. It consists of 120 hybrid silicon pixel detectors modules with a total of ~10^7 cells. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The control room located read-out electronics is housed in 20 VME boards and builds the interface to the ALICE trigger, data acquisition and control system. In this contribution the detector components design and production are reviewed. The detector commissioning and experience during first operation are presented.
        Speaker: Dr Alex Kluge (CERN)
        Paper
        Slides
      • 52
        Installation, Commissioning and Performance of the CMS Electromagnetic Calorimeter Electronics
        This talk reviews the CMS high resolution electromagnetic calorimeter (ECAL) on- and off-detector electronics and its commissioning within CMS in-situ. In particular it presents results on electronics noise, monitoring, dead channels and performance , together with the experience gained during installation. The talk will also include results from the first months of ECAL operation during the commissioning of LHC.
        Speaker: Nicolo Cartiglia (Univ. + INFN)
        Paper
        Slides
      • 53
        Installation and Commissioning of the ATLAS LAr Read-Out Electronics
        The cryostats of the ATLAS LAr calorimeter system are installed in the ATLAS cavern since several years. Following this, an effort to install and commission the front end read-out electronics (infrastructure, crates, boards) has been ongoing and is finished now, in time for the cavern closure. Following cautious procedures and with continuous testing-campaigns of the electronics at each step of the installation advancement, the result is a fully commissioned calorimeter with its readout and a small number of non-functional channels. A total of only 0.017% of the read out channels is dead and 0.4% need special treatment for calibration. The presentation will give a general overview of the installation and refurbishment campaign of the ATLAS LAr calorimeter electronics and show results of the calibration runs that were taken continuously during the various phases of commissioning. Different problems observed and addressed will be discussed. It will describe noise studies that have been performed and shortly review the solutions implemented to reduce noise. The excellent stability of the calorimeter readout will be demonstrated by showing results from pedestal and pulse height studies.
        Speaker: Guy Perrot (Laboratoire d'Annecy-le-Vieux de Physique des Particules (LAPP))
        Paper
        Slides
    • Parallel Session B3 - Machine-Experiment, BCM
      • 54
        Fast Beam Conditions Monitoring (BCM1F) for CMS.
        The CMS Beam Conditions and Radiation Monitoring System (BRM) is composed of different subsystems that perform monitoring of, as well as providing the CMS detector protection from, adverse beam conditions inside and around the CMS experiment. This paper presents the Fast Beam Conditions Monitoring subsystem (BCM1F), which is designed for fast flux monitoring based on bunch by bunch measurements of both beam halo and collision product contributions from the LHC beam. The BCM1F is located inside the CMS pixel detector volume close to the beam-pipe and provides real-time information. The detector uses sCVD (single-crystal Chemical Vapor Deposition) diamond sensors and radiation hard front-end electronics, along with an analog optical readout of the signals.
        Speaker: Mr Vladimir Ryjov (CERN)
        Paper
        Slides
      • 55
        The ATLAS Beam Condition Monitor Commissioning
        The ATLAS Beam Condition Monitor (BCM) based on radiation hard pCVD diamond sensors and event-by-event measurements of environment close to interaction point (z=+/-184 cm, r=5.5 cm) has been installed in the Pixel detector since early 2008 and together with the Pixel detector in the ATLAS cavern since June 2007. The sensors and front end electronics was shown to withstand 0.5 Mrad and 10^15 particles/cm^2 expected in LHC lifetime. Recently the full readout chain, partly made of radiation tolerant electronics, still inside of the ATLAS spectrometer and partly in the electronics room, was completed and the system is now ready for the first LHC single beams as well as first collisions this summer.
        Speaker: Dr Andrej Gorisek (J. Stefan Institute, Ljubljana, Slovenia)
        Paper
        Slides
      • 56
        The ATLAS Radiation Dose Measurement System and its Extension to SLHC Experiments
        In LHC experiments, a precise measurement of the radiation dose at various detector locations is crucial. In ATLAS, this task is performed by a set of radiation monitors (RADMON) which are able to record Non-Ionising Energy Loss (NIEL), the Total Ionizing Dose (TID) and measure fluences of thermal neutrons. These measurements are vital for understanding the changes in detector performance during ATLAS operation, verifying simulations and optimising the operation scenario. The RADMONs are multi-sensor boards, containing several RADFETs, diodes and DMILL transistors. It is clear that a similar system will be of even greater importance for SLHC environments due to the increased radiation dose.
        Speaker: Mr Jochen Hartert (University of Freiburg)
        Paper
        Slides
    • Parallel Session B4 - Interconnects
      • 57
        The Origami Chip-on-Sensor Concept for Low-Mass Readout of Double-Sided Silicon Detectors
        Modern front-end amplifiers for silicon strip detectors offer fast shaping but consequently are susceptible to input capacitance which is the main contribution to the noise figure. Hence, the amplifier must be close to the sensor which is not an issue at LHC, but a major concern at material budget sensitive experiments such as Belle or the ILC detector. We present a design of a silicon detector module with double-sided readout where thinned front-end chips are aligned on one side of the sensor which allows efficient cooling using just a single, thin aluminum pipe. The connection to the other sensor side is established by thin kapton circuits wrapped around the edge - hence the nickname origami.
        Speaker: Markus Friedl (Institute of High Energy Physics (HEPHY))
        Paper
        Slides
      • 58
        PMF the front end electronic for the ALFA detector
        The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on few PMFs have showed performances in good agreement with the requirements.
        Speaker: Dr Christophe de La Taille (IN2P3/LAL Orsay)
    • 13:30
      Short Lunch
    • Parallel Session A5 - Installation & Commissioning
      • 59
        The LHCb Silicon Tracker: lessons learned (so far)
        The LHCb Silicon Tracker is part of the main tracking system of the LHCb detector. It covers the full acceptance angle in front of the dipole magnet in the Trigger Tracker station and the innermost part in the three Inner Tracker stations downstream of the magnet. We report on final elements of the production, the installation and commissioning process in the experiment. Focusing on electronic and hardware issues we describe the lessons learned and the pitfalls encountered. First experience of detector operation is presented.
        Speaker: Dr Achim Vollhardt (Universitat Zurich)
        Paper
        Slides
      • 60
        SCT Commissioning
        The Barrel and EndCaps of the ATLAS SemiConductor Tracker have been installed in the ATLAS cavern since summer 2007. All the electrical and optical services were connected and rapid tests performed to verify their continuity. Problems with the cooling circuits, meant that the time for detailed tests in 2007 was limited. These problems have now been resolved allowing the SCT to be operated and participate in combined ATLAS Cosmic ray data taking runs. The results of these runs have been used to determine the hit efficiency of the modules as well as providing invaluable constraints for the detector alignment.
        Speaker: Mrs Caroline Magrath (Radboud University,)
        Paper
        Slides
      • 61
        Studies of the Assembled CMS Tracker
        During the latter months of 2006 and the first half of 2007, the CMS Tracker was assembled and operated at the Tracker Integration Facility in Building 186 at CERN. During this time, several dedicated studies were carried out to validate the performance of the tracker after assembly, testing general noise performance, potential interference between subdetectors, and performance at high acquisition rates. We report on the the results of these studies and their consequences for operation of the Tracker at the experiment.
        Speaker: Mr Pieter Everaerts (Massachusetts Institute of Technology)
        Paper
        Slides
      • 62
        CMS Tracker Services: present status and potential for upgrade
        A report is given on the completed programme of installation, connection and testing of the CMS Tracker services, culminating in the full checkout of the Tracker as an integrated system. Finally, in the context of future upgrades to the CMS Tracker, we report also on the potential capacity and constraints of re-using the current services.
        Speaker: Mr Robert Stringer (Department of Physics - University of California)
        Paper
        Slides
    • Parallel Session B5 - Power
      • 63
        Custom DC-DC converters for distributing power in SLHC trackers
        The tenfold increase in the number of channels in SLHC trackers, and the wish to actually decrease the material budget to improve the physics performance of the detectors, set uncomfortable limits for the on-detector power budget. A power distribution system based on DC-DC converters has the potential to contribute significantly to the drastic reduction in wasted power necessary to meet these limits. A possible distribution scheme, based on two stages of conversion performed by custom-developed components, is discussed together with the main technical challenges for the development of these components.
        Speaker: Stefano Michelis
        Paper
        Slides
      • 64
        System test with DC-DC converters for the upgrade of the CMS silicon strip tracker
        Due to the increase in granularity and higher complexity of the front end electronics needed at the SLHC, an upgrade of the CMS silicon strip tracker is expected to require even more power than the current CMS strip tracker. However, the space available for cables will remain the same as today. In addition, a further increase of the material budget due to cables and cooling is not acceptable from the physics point of view. Novel powering schemes such as serial powering or usage of DC-DC converters have been proposed to solve the problem. Since custom DC-DC converters that satisfy the requirements of radiation hardness and magnetic field tolerance are not available yet, we have operated substructures of the current CMS strip tracker with off-the-shelf DC-DC converters. These devices have been integrated into the CMS tracker hardware and the system performance, in particular the noise behaviour, has been studied. The results of this first operation of CMS strip modules with DC-DC converters will be presented and discussed.
        Speaker: Dr Katja Klein (I. Physikalisches Institut (B))
      • 65
        Design Considerations for High Step Down Ratio Buck Regulators
        Buck topology is the workhorse in most of the power electronic devices. Buck converter is step-down DC to DC converter. It utilizes two switches (two FETS or one FET and one diode) along with an output inductor and output capacitor. Whether you look at the large computer server, personal computer Desktop or laptop, cell phone or GPS unit all will contain a buck topology design in one form or the other.
        Speaker: Mr Ramesh khanna (National Semiconductor Corp.)
        Paper
        Slides
      • 66
        Serial Powering of Silicon Strip Modules for the ATLAS Tracker Upgrade
        The costs, difficulties and inefficiencies associated with the cabling of silicon detector systems are well known. Serial Powering is an elegant solution to these issues and is being actively pursued by the ATLAS Tracker upgrade community. Demonstrator supermodules have been produced using the ABCD chip from the present ATLAS SCT together with serial powering circuitry built from commercial components. Two 6 module supermodules have been built, and construction of a third supermodule to a 30 module desgin is in progress. Recent results from these supermodules will be presented. Elements of the serial powering scheme have been incorporated into new ASIC designs, and studies of system issues such as protection schemes have advanced greatly. Time permitting, these developments and their application to the next demonstrator supermodule will also be outlined.
        Speaker: Mr Peter Phillips (Particle Physics)
        Paper
        Slides
    • 15:55
      Break
    • Parallel Session A5 - Installation & Commissioning
      • 67
        The electronics of ALICE Dimuon tracking chambers
        The Alice Muon Spectrometer tracking system is composed of five stations (ST) with two wires chambers each. IPN Orsay is responsible for the electronics design and production for the tracking (1.1M channels), for the readout electronics software and for the ST1 design and building. We will describe the readout architecture based on dedicated Front-End boards, embedded digital crates, and a Trigger crate. We will explain the process to reach the final electronic design. We will describe the electronics production, specially the tests for the 20000 Front-End boards. We will focus on ST1 integration at CERN, EMC issues and commissionning.
        Speaker: Dr Valerie Chambert (IPN Orsay)
        Paper
        Slides
      • 68
        Readout Electronics of the ATLAS Cathode Strip Chambers
        The ATLAS muon spectrometer employs cathode strip chambers (CSC) to measure high momentum muons in the forward regions (2.1 < |\eta| < 2.7). Due to the severe radiation levels expected in this environment, the on-detector electronics are limited to amplifying and digitizing the signal while sparsification, event building and other tasks are performed off-detector. We report on the commissioning of the CSC readout electronics and its integration into the ATLAS detector.
        Speaker: Ivo Gough Eschrich (UC Irvine)
        Paper
        Slides
      • 69
        Design and commissioning of the ATLAS Muon Spectrometer RPC Read Out Driver
        The RPC subsystem of the ATLAS muon spectrometer provides the Level-1 trigger in the barrel and it is read out by a specific DAQ system. On-detector electronics pack the RPC data in frames, tagged with an event number assigned by the trigger logic, and transmit them to the counting room on optical fibre. Data from each sector are then routed together to a Read-Out Driver (ROD) board. This is a custom processor that parses the frames, checks their coherence and builds a data structure for all the RPCs of one of the 32 sectors of the spectrometer. Each ROD sends the event fragments to a Read-Out subsystem for further event building and analysis. The ROD is a VME64x board, designed around two Xilinx Virtex-II FPGAs and an ARM7 microcontroller. In this paper we describe the board architecture and the event binding algorithm. The boards have been installed in the ATLAS USA15 control room and have been successfully used in the ATLAS commissioning runs.
        Speaker: Dr Vincenzo Izzo (Universita di Napoli Federico II and INFN, sez. di Napoli)
        Paper
        Slides
    • Parallel Session B5 - Power
      • 70
        The SPI as an integrated power management device for serial powering
        For future hep experiments, especially for LHC upgrades new powering schemes are required. The SPI001 (Serial Powering Interface) chip has been designed and fabricated to explore the serial powering approach. Main features of the chip are a programmable shunt regulator (handling at least 1A) and two linear regulators providing module voltages, current mode ADCs monitoring shunt and linear regulator current, overpower protection and AC coupled communication interfaces. Bump bonding techniques are used for chip on board assembly to enhance connectivity and thermal issues. The concept and design details of the chip are presented and first results are shown.
        Speaker: Marcel Trimpl (Fermilab)
        Slides
      • 71
        The Power System Detector Control System of the Monitored Drift Tubes of the ATLAS Experiment
        The Detector Control System (DCS) of the power supply of the Monitored Drift Tubes (MDT) detector of the ATLAS experiment at CERN will be presented. The principal task of DCS is to enable and ensure the coherent and safe operation of the detector. The interaction of detector experts, users or even shifters with the detector hardware is performed via DCS. This is the responsible system of monitoring the operational parameters and the overall state and status of the detector, the alarm generation and handling, the connection of hardware values to databases and the interaction with the Data Acquisition system. The MDT subdetector was treated as a Finite State Machine hierarchy while the operation is done on a top level human interface. The Power System (PS) for the High & Low Voltage of the DCS in ATLAS is implemented using the SY1527 power system with the Easy crate configuration from CAEN. The readout was done via an OPC server.
        Speaker: Theodoros Alexopoulos (National Technical University of Athens)
        Paper
        Slides
      • 72
        Noise Susceptibility Measurements of Front-End Electronics Systems
        The conducted and radiated noise that is emitted by a power supply constrains the noise performance of the front-end electronics system that it powers. The characterization of the noise susceptibility of the front-end electronics allows setting proper requirements for the back-end power supply in order to achieve the expected system performance. A method to measure the common mode current susceptibility using current probes is presented. The compatibility between power supplies and various front-end systems is explored.
        Speaker: Mr Georges Blanchot (CERN)
        Paper
        Slides
    • POWER WORKING GROUP
      • 73
        Introduction
        Speaker: Philippe Farthouat (CERN)
      • 74
        Critical areas and ATLAS next steps
        Speaker: Marc Weber (Rutherford Appleton Laboratory)
        Slides
      • 75
        Commercial DC-DC
        Speaker: Dr Satish Dhawan (Yale University)
        Slides
      • 76
        Technologies for a DC-DC ASIC
        Speaker: Federico Faccio (CERN)
        Slides
      • 77
        Progress on DC/DC Converters Prototypes
        Speaker: Stefano Michelis
        Slides
      • 78
        Enpirion radiation test results
        Speaker: Mr Matt Stettler (CERN)
      • 79
        Discussion
    • 19:30
      Scientific Committee Meeting
    • 20:30
      Committee Dinner
    • Plenary Session 6 - LHC upgrades: needs and reality
      • 80
        Overview and Electronics Needs of ATLAS and CMS High Luminosity Upgrades
        The LHC will start up in 2008 and ramp up in luminosity over 3 years to 10^34 cm^-2 s^-1. A series of machine upgrades will continue to increase this, eventually reaching 10^35 cm^-2 s^-1 around 2018. This talk summarises the physics possibilities that high luminosity will open up, and then describe the changes needed to ATLAS and CMS to meet the challenges of the high pile-up of overlapping events and radiation background. Electronics advances are needed throughout the detector and will be emphasized.
        Speaker: Dr Nigel Hessey (NIKHEF)
        Open Document Format
        Paper
        Powerpoint format
        Slides
      • 81
        CO2 cooling for HEP experiments
        The new generation silicon detectors in High Energy Physics (HEP) Experiments require more efficient cooling of the front-end electronics and the silicon sensors itself. To minimize reverse annealing, the silicon sensors must be cooled down to a temperature of about -5°C. Other important requirements of the new generation cooling systems are a low mass and a maintenance free operation of the hardware inside the detector. Evaporative CO2 cooling systems are ideal for this purpose as they need smaller tubes than systems with Fluor Carbons. The heat transfer capability of evaporative CO2 is high and CO2 is radiation hard. CO2 is used as cooling fluid for the LHCb-Velo and the AMS-Tracker cooling systems. A special method for the fluid circulation is developed at NIKHEF in order to get a very stable temperature of both detectors without any active components like valves or heaters inside the detector. This method is called 2-Phase Accumulator Controlled Loop (2PACL) and is a good candidate technology for the design of the future cooling systems for the Atlas and CMS upgrades. In this paper the design and the test results of the LHCb-VELO CO2 cooling system are discussed and a comparison is made between the use of Fluor Carbons and CO2 in a typical HEP detector application
        Speaker: Mr Bart VERLAAT (NIKHEF)
        Paper
        Slides
    • 10:30
      Break
    • TOPICAL 1 - LHC Upgrades
      • 82
        SLHC Upgrade Plans for the ATLAS Pixel Detector.
        The ATLAS Pixel Detector is an 80 M channels silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. An upgrade is presently being considered for the ATLAS Pixel Detector, enabling to cope with higher luminosity at Super-LHC (SLHC). Options considered for a new detector are discussed, as well as some important R\&D activities, such as investigations towards novel detector geometries and novel processes.
        Speaker: Petr Sicho (Elementary Particle Division - Institute of Physics - Acad. of S)
        Paper
        Slides
      • 83
        Design studies of a low power serial data link for a possible upgrade of the CMS pixel detector
        The material budget inside the sensitive tracking volume is highly dependent on the dissipated power for data transmission. It is therefore important to have a very low power serial data link, that allows to transmit digital data over short distances within the tracking volume. Such a low power ohmic data transmission through micro-twisted transmission lines aims for a transmission speed of 160/320 MHz and allows to concentrate the tracker data to multi gigabit optical data hubs. For such a future link we need low swing differential drivers and receivers with PLLs for frequency multipliers and clock recovery. We have implemented in radiation hard layout all the necessary components on a recently submitted 250nm CMOS test chip. After reporting on the experience gained with low power data transmission in the current CMS pixel detector we present the design considerations and first results for this new 160/320 MHz serial link that may work with differential signal levels as low as 10mV.
        Speaker: Mr Beat Meier (Paul Scherrer Institut, Chip Design Group)
        Paper
        Slides
      • 84
        Architecture of the readout electronics for the ATLAS upgraded tracker
        The upgrade of luminosity of the LHC (SLHC) will necessitate changing the ATLAS tracker. The new fully silicon tracker will contain pixel layers, short-strip layers and long-strip layers. The silicon strip detector will be organized in staves or super-modules. The readout electronics will follow this organization and be based on front-end ICs, module controllers and super-module controllers. This presentation will describe the proposed readout architecture, the different options for powering the front-end electronics and for controlling the detector, as well as the on-going developments.
        Speaker: Philippe Farthouat (CERN)
        Paper
        Slides
      • 85
        CMS microstrip tracker readout at the SLHC
        The increased luminosity at the SLHC and associated increases in occupancy and radiation levels present severe challenges for the CMS tracker, which will require complete replacement. Inner pixellated regions will expand to higher radii and the outer tracker region will most likely be instrumented with short strip silicon sensors. It is also necessary for the tracker to provide information to the level 1 trigger. Power consumption is one of the main challenges for the tracker readout system, because of the higher granularity. We will present the current status of readout chip development for a short strip outer tracker, with projections for performance and power consumption.
        Speaker: Mark Raymond (High Energy Phys.Group Blackett-Lab Imp.Coll.)
        Paper
        Slides
      • 86
        Upgrade of the ATLAS Monitored Drift Tube Detector for the SLHC
        The upgrade of the LHC towards higher luminosity needs to be matched by an upgrade of the detector performance. In the case of the ATLAS Monitored Drift Tube (MDT) detectors, higher luminosity will result in increased neutron and gamma background rates leading to a reduction of spatial resolution and tracking efficiency as well as to an increase of the required readout bandwidth. In the regions of highest background rates (forward region) a modified detector and readout concept will probably be necessary to maintain tracking efficiency and to limit the data volume due to background hits. We will present an overview of the upgrade options for the MDT chambers and their readout electronics.
        Speaker: Robert Richter (Max-Planck-Institut fur Physik)
        Paper
        Slides
    • 13:05
      Lunch
    • TOPICAL 2 - LHC Upgrades
      • 87
        Lessons from LHC
        Twenty years ago the embryonic LHC Collaborations were trying to understand how to do experiments at the next generation of proton colliders. In particular, the electronics communities were faced with a number of difficult problems. Some problems were associated with the choice of technologies, some with adapting emerging technologies to the Particle physics environment, and some were associated with engineering very complex systems with limited resources. This year, the electronics systems that were engineered for the LHC experiments have been successfully commissioned, and the community has started to contemplate the challenges of upgrading some of these systems for Super LHC (SLHC). It is timely to reflect on what was has been learned from the engineering the LHC electronics systems and to consider possible future improvements.
        Speaker: Peter Sharp (CERN)
        Slides
      • 15:00
        Discussion - J. Christiansen
    • 15:50
      Break
    • POSTERS SESSION
      slides
      • 88
        14-bit and 2GS/s low-power digitizing boards for physics experiments
        The new Matacq14 board described in this paper has been designed to digitize 4 channels with 14 bits of resolution at 2 GS/s with an analog bandwidth of 345 MHz. It is not based on commercial ADCs which don’t reach these specifications, but on the low-power custom-designed analog circular memory called MATACQ. It can be triggered internally or externally, and several boards can easily be synchronized. It integrates USB, GPIB and 64-bit VME interfaces, permitting complying with most current acquisition systems. It can thus replace oscilloscopes for a lower cost in most applications where a much higher precision is needed.
        Speaker: Mr Dominique Breton (Laboratoire de l''Accelerateur Lineaire (LAL) (IN2P3) (LAL))
      • 89
        A dual scale 1mW full flash ADC for the ILC vertex detector
        The resolution needed in the CMOS sensors of the ILC vertex detector implies a digitization of each pixel by a small, 4-5 bits, dedicated ADC. The ADC characteristics, given by the constraints of the pixel matrix and its read out are for one ADC per column : 10 MS, 25 micron width and about 1mW consumption, thank to the fact that this power could be turn off 99 % of the time. To fit these requirements, several architectures were designed in different laboratories. This paper describes the results of the LPC Clermont Ferrand R&D witch is a two scales, 20 MS,1mW, 47 µm width, full flash ADC sharing two columns.
        Speaker: gerard bohner (LPC Clermont Ferrand)
      • 90
        A front end chip for the INNOTEP project including a 8 bits, 100 MS ADC.
        This paper describes the front end electronic developed for the IN2P3 INNOTEP project by the pole microelectronic Rhone Auvergne. (Collaboration LPC Clermont Ferrand and IPNL Lyon). This circuit handles the signals coming from LSO crystals trough photo detectors (APD, PM...), and has to provide energy and time measurement, with medium accuracy (8 bits) for the energy but very high accuracy (500 ps at least) for the time. The electronic consist of a high gain charge amplifier, a fast shaper and a pipe line ADC. Two versions of charge amplifier and shaper were realized and tested, the ADC is under development, its first version should be send to foundry in June. This ADC is 4 stages, 2.5 bits per stage pipe line, with open loop track and holds and amplifiers. It is design in SiGe 0.35µm technology.
        Speaker: Sebastien crampon (LPC Clermont Ferrand)
      • 91
        A GOL Based Optical Demo Link to Study System Issues for the ATLAS Inner Detector Readout Upgrade
        The GOL ASIC is a serializer chip developed by CERN based a 0.25 μm CMOS technology. The GOL operates with two data rate: 800 Mbps and 1.6 Gbps. This ASIC has been evaluated for the ATLAS Inner Detector readout upgrades for the SLHC. A demo link is being designed to read out test staves through fiber optics and study system issues in a giga-bit optical link. The results of the radiation evaluation and the demo-link will be reported.
        Speaker: Prof. Jingbo Ye (Southern Methodist Univeristy)
        Paper
      • 92
        A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
        A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and submitted for fabrication in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.
        Speaker: Mr Christian Mester (CERN)
        Paper
      • 93
        A prototype ASIC buck converter for LHC upgrades
        Given the larger number of channels and the need for reduced material budget in the SLHC trackers, alternatives to the present power distribution scheme have to be explored. In this context we are envisaging a new architecture based on custom switching converters able to work in the high radiation and high magnetic field environment of the experiments. A prototype of the converter has been designed and integrated in an ASIC. This includes the fundamental building blocks of a buck converter that can be used in later and more complete designs and even in different topologies. Design techniques, functional and radiation tests of the prototype will be discussed.
        Speaker: Mr Stefano Michelis (CERN)
        Paper
        Poster
      • 94
        A Prototype of Low Voltage Power Supply Using Piezoelectric Transformer
        A prototype of the low voltage power supply is implemented with a piezoelectric transformer provided by Tokin Corporation lately, where the piezoelectric transformer realizes ground isolation between the primary and the secondary. The low voltage power supply, integrating the piezoelectric transformer, produces the regulated output voltage of 1.5 V from the supply voltage around 48 V. A carrier drives the piezoelectric transformer where the carrier is generated by a full bridge of FETs operated in a phase shift mode. The full-bridge phase shift switching realizes flexible control over the frequency and the amplitude of the carrier. The carrier is converted in amplitude by the transformer, and then rectified to be the output voltage of the power supply, which is fed back to the frequency and the amplitude of the carrier. The response of the output voltage is improved by the feedback. The output voltage is stabilized by feedback. A feedback loop includes error amplifiers, FETs and a control IC for the full-bridge phase-shift switching. The control IC includes the circuitry necessary for the feedback, generating gate drive signals for FETs. The error amplifier detects the deviation of the output voltage from a reference voltage, supplying error signals to the control IC, The error signal changes the timing of the gate drive signals, thus modifying the amplitude of the carrier. The error signal also changes the switching frequency of the control IC, thus shifting the frequency of the carrier.
        Speaker: Masatosi Imori (ICEPP, University of Tokyo)
      • 95
        A Radiation Tolerant Current Reference Circuit in a standard 0.13um CMOS Technology.
        A Current-summing Bandgap reference circuit, has been developed in a 0.13um CMOS technology. The reference current has low sensitivity to temperature and power supply variations. In the design we utilize only CMOS structures (instead of diodes) and poly-silicon resistors. The combination of the natural properties of the thin gate oxide MOS transistors with gate-all-around layout, results in a circuit having a very low susceptibility to ionizing radiation. The output current varies in the range +- 0.9% when the circuit is being irradiated up to dose of 200 Mrad.
        Speaker: Vladimir Gromov (NIKHEF)
        Paper
      • 96
        A small portable test system for the TileCal Digitizer system
        The TileCal hadron calorimeter in the ATLAS detector contains about 2000 digitizer boards, developed and maintained by Stockholm University. A rather complex test system has until now been used to verify the functionality of the boards. However, it was built almost 10 years ago and is now in itself difficult to maintain since it consists of several already obsolete parts. The development of a new simple, reliable and portable test system that could survive the digitizers was therefore initiated. Its components have been chosen to reduce the problem with obsolescence and to allow easy migration to new platforms.
        Speaker: Mr Attila Hidvegi (Stockholm University - Physics Dept.)
        Paper
        Poster
      • 97
        Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
        The double edge Source Synchronous Transfer (2eSST) is the fastest block transfer cycle offered by the VME64x standard. The maximum achievable data-rate foreseen by the protocol is 320 Mbyte/s. In this paper we present a reference design based on a FPGA for the reader willing to implement 2eSST in his VME64x application. By using this template, we have designed a custom Bit Error Rate Tester, in order to probe the block transfer reliability within and beyond the data rate limit presently set by the standard. Our results show that 800 Mbyte/s data transfers can be achieved in a 21 slots crate with a BER smaller than 10^-12.
        Speaker: Raffaele Giordano (Universita’ di Napoli ‘Federico II’ and INFN Sezione di Napoli, Napoli (Italy))
        Paper
      • 98
        ATLAS Level-1 Level-2 Trigger Integration Commissioning
        The ATLAS detector will be exposed to proton proton collision at the center of mass energy of 14 TeV with the bunch crossing rate of 40 MHz. In order to reduce this rate down to the level at which only interesting events will be fully reconstructed, a three-level trigger system has been designed. The level 1 (LVL1) trigger reduces the rate down to 75 kHz via the custom-built electronics. The Region of Interest Builder (RoIB) delivers the Region of Interest (RoI) records to the level 2 (LVL2) trigger which runs the selection algorithms with the commodity processors and brings the rate further down to ~3 kHz. Finally the Event Filter (EF) reduces the rate down to ~200 Hz for permanent storage. The LVL1, LVL2 systems will be overviewed. The commissioning in situ using almost full detectors, the full trigger system and the DAQ system will be discussed. Results on system functionality and performance based on the cosmic data will be presented. Some studies on system scalability and reliability will be shown with preselected simulated events running through the trigger and dataflow system.
        Speaker: Dr Jinlong Zhang (Argonne National Laboratory (ANL))
        Paper
      • 99
        Characterization of the noise properties of DC to DC converters for the sLHC
        The upgrade of the LHC experiments sets new challenges for the powering of the detectors. One of the powering schemes under study is based on buck converters mounted on the front-end modules. The switching noise emitted by these converters is susceptible to affect the performance of the powered systems. A model to identify and to control the noise sources of the converter was developed. A reference test setup with associated measurement methods is used to characterize the noise properties of the converter. Complementary tools and simulations were also used to evaluate the noise couplings at system level.
        Speaker: Mr Georges Blanchot (CERN)
        Paper
        Poster
      • 100
        CMS ECAL LV Control System performance
        The CMS ECAL Low Voltage system is made of 136 WIENER MARATON power supplies, delivering about 250kW of power to the on-detector electronics. The system is controlled by the PVSS-based Detector Control System (DCS), which communicates with the MATATON local controllers via 11 CANbus brunches. The stability of the 2.5V power, delivered to the Very-Front-End electronics is controlled by the DCU readout, accessible via DAQ - Control Token Ring chain. The setup parameters and the system status has to be read/stored from/to the Detector Configuration/Conditions data bases. The overall control system performance, as well as the performance of each component will be analyzed. The timing and reliability of the Framework - PVSS-OPC server-Local controller chain will be presented. Connection to the DAQ for the DCU readout and status display will be discussed.
        Speaker: Alexander Singovski (Tate Lab.of Physics, High Energy Physics)
      • 101
        CMS Tracker, ECAL and Pixel Optical Cabling: Installation and Performance verification
        The installation of over 55000 optical links for the readout and control of the CMS Tracker, ECAL and Pixel detectors is now completed at CERN LHC Point 5. During the 2007 cabling campaign 672 optical cables that span between the experimental and service caverns were installed and tested. The connection to the optical, highly dense, patch-panels inside CMS followed in the first months of 2008. Within the quality control programme, an extensive test campaign was carried out in parallel in order to validate the cabling and connection process and feedback any improvements. In the end 99% of the failures were recovered and the Tracker, in particular, resulted with 0.13% of not working channels. For the Tracker, a verification of the optical link performance followed once the detector was powered-up and commissioned.
        Speaker: Mr Daniel Ricci (CERN)
        Paper
      • 102
        Commissioning of the SDD data concentrator card CARLOSrx
        The data concentrator card CARLOSrx is a readout board developed for the ALICE ITS Silicon Drift Detector (SDD) experiment held at CERN. CARLOSrx is a 9Ux400 mm VME board, containing 4 FPGAs with the purpose of processing data coming from 12 SDD detectors and sending them to a computer running the DATE software. We have 24 CARLOSrx installed at CERN, each CARLOSrx is able to receive data from 12 SDD detectors, so we are able to read the data produced by all the SDD detectors. This paper presents the results obtained during the runs performed at CERN.
        Speaker: Dr Filippo Costa (Department of Physics & INFN Bologna)
      • 103
        Commissioning the CMS silicon strip tracker
        The CMS silicon strip tracker is the largest device of its type ever built for the detection of charge particles produced in beam-beam collisions. There are 24244 single-sided micro-strip sensors covering an active area of over 200 square meters and nearly ten millions of readout channels. The sub-detector was installed inside CMS in December 2007. We report on detector performance studies from the commissioning phase, when the complete readout system was calibrated and synchronized for the first time, and on experiences from global cosmic runs with other sub-detectors of the CMS experiment.
        Speaker: Dr Robert John Bainbridge (HEP group, Imperial College London)
      • 104
        Completion of the CMS Muon Barrel Alignment System and its integration into the CMS detector environment.
        During the past years our group has built, calibrated, and finally installed all the components of the Muon Barrel Alignment System of the CMS experiment. This paper covers the results of the hardware commissioning, the full system setup and the connection to the CMS Detector Control System (DCS). The step-by-step operation of the system is discussed: from collecting the analog video signals and preprocessing the observed LED images, through to controlling the front-end PCs and forming the measurement results for the CMS DCS. The first measurement results and the initial experiences of the communication with the DCS are also discussed.
        Speaker: Dr Géza Székely (MTA Atomki, Debrecen, Hungary)
        Paper
      • 105
        Control, test and monitoring software framework for the ATLAS Level-1 Calorimeter Trigger
        The ATLAS first-level calorimeter trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates and to measure total and missing ET in the ATLAS calorimeters. The complete trigger system consists of over 300 custom designed VME modules of varying complexity. These modules are based around FPGAs or ASICs with many configurable parameters, both to initialize the system with correct calibrations and timings and to allow flexibility in the trigger algorithms. The control, testing and monitoring of these modules requires a comprehensive, but well-designed and modular, software framework, which we will describe in this paper.
        Speaker: Dr Murrough Landon (Queen Mary, University of London)
        Paper
      • 106
        DAQ and Control Systems for the CMS Global Calorimeter Trigger Matrix Processor
        A new trigger component based on the uTCA standard is being developed for the CMS Global Calorimeter Trigger (GCT). The new system is designed to handle the exchange of data between GCT and the Global Muon Trigger and is called the GCT Muon System. The GCT muon system consists of a uTCA crate with a custom uTCA backplane instrumented with several Matrix processor cards, which use a Xilinx Virtex-5 FPGA and an M21141 72x72 cross-point switch. We discuss the development and use of the various communication systems available for the Matrix processor. Given the nature of the Virtex-5 FPGAs used as the basis of the design, there are several communication protocols available. In this paper we focus on the use of PCI express and Gigabit Ethernet UDP/IP using the built-in Virtex-5 interfaces, and TCP/IP and IPMB via an NXP microcontroller interface on the Matrix board itself. The use of these interfaces for slow control of the board and fast Data AcQuisition (DAQ) are discussed in terms of available bandwidth and resource usage. Furthermore we discuss the implications of the use of such industry-standard interfaces as a replacement for more traditional simplex busses such as VME. To that end we outline the development of a new Hardware Abstraction Layer (HAL) with built-in overlapped I/O and one possible serial bus architecture providing a metastability-tolerant interface and auto-discovery for ease of use.
        Speaker: Mr Jad Marrouche (Imperial College London)
      • 107
        Data Acquisition System for the KL Experiment at J-Parc
        We present the proposed Data Acquisition (DAQ) System for the KL Experiment at J-Parc, Japan. It comprises three distinctive flavors of 6U VME boards: a 14-bit, 125 MHz ADC module for reading out an approximately 3000-channel Cesium-Iodide (CsI) detector; a 12-bit, 500 MHz ADC module for reading out a 100-channel Beam Hole Phase Veto (BHPV) detector; and a digital Trigger module able to provide a detector-wise synchronous energy sum. The Csi Calorimeter readout board amplifies analog pulses from 16 photomultipliers and passes them through a 10-pole shaper before digitizing. Data are then processed locally with field programmable gate arrays (FPGAs) to determine real-time energy values for the system Trigger Supervisor. The ADC module is provided with a pipeline, up to 4us long, which stores the acquisitions, awaiting the system trigger pulse. After a trigger, data are packed and buffered for readout via the VME32/64 backplane. The full design and preliminary test results will be described
        Speaker: Mr Mircea Bogdan (The University of Chicago)
        Paper
      • 108
        Data acquisition systems for future calorimetry at the International Linear Collider
        A data acquisition system is described which will be used for the next generation of prototype calorimeters for the ILC. The design is sufficiently generic such that it should have applications elsewhere, be they other ILC detectors or elsewhere within physics. An under-pinning thread is the use of commercial components. Therefore the system should be easily upgradeable, both in terms of ease of acquiring new components and competitive prices. Results and tests already done will then be shown indicating the potential of the approach. The status of the system to read out prototypes in 2009 will be discussed.
        Speaker: Matthew Wing (UCL)
      • 109
        DC- DC Power Conversion with Voltage Ratios > 10 for LHC Upgrade Detectors DC- DC Power Conversion with Voltage Ratios > 10 for LHC Upgrade Detectors
        Our group is researching commercial power converters having voltage ratios greater than ten that are capable of running in the ATLAS Silicon Tracker high luminosity upgrade environment. The devices therefore must operate in a high magnetic field (2 T) and be radiation hard to ~50-100 MRad and ~ 1015 neq/cm2. These converters are to be mounted on the same multi-chip modules as the ASIC readout chips or in close vicinity without introducing any additional readout noise due to the MHz switching frequencies. Such devices will permit higher voltage power delivery to the tracker and thus increase overall power efficiency by limiting the ohmic losses in the ~100 meters of cable between the tracker and the power sources.
        Speaker: Dr Satish Dhawan (Yale University)
        Paper
      • 110
        Design and measurements of SEU tolerant latches.
        The single event upset (SEU) tolerance of various latch designs in 0.13um CMOS technology has been studied by both measurement and simulation. The aim of this work is to optimize the design for critical registers on the next generation pixel readout chip for ATLAS upgrades (denominated FE-I4). Results form irradiations with 24 GeV protons will be presented and compared to previous values obtained with heavy ions. Layout effects will be discussed and quantified along with other design considerations.
        Speaker: Mohsine Menouni (Unknown)
        Paper
      • 111
        Design Considerations for Area-Constrained In-Pixel Photon Counting in Medipix3
        Medipix3 is a single photon-counting hybrid pixel detector which records the discrete number of photons incident on a pixel. It aims to diminish the effects of charge diffusion across the sensor volume by considering the total charge collected by all pixels within a local neighbourhood during the evaluation of a charge event. The integration of multiple functions within the compact pixel area requires the manual layout of custom transistors, optimizing their physical placement and connections using non-standard techniques. This work describes various area-saving design strategies to optimize the use of available space in the digital section of the Medipix3 pixel.
        Speaker: Ms Winnie Wong (CERN)
        Paper
      • 112
        Detector Control System for the electromagnetic calorimeter in the CMS experiment – summary of the first operational experience.
        A full scale implementation of the Detector Control System (DCS) for the electromagnetic calorimeter (ECAL) in the CMS experiment is presented. The operational experience from the ECAL commissioning at the CMS experimental cavern and from the first ECAL and global CMS data taking runs is discussed and summarized.
        Speaker: Diogo Di Calafiori (ETH Zurich, Switzerland)
        Paper
        Poster
      • 113
        Detector noise susceptibility issues for the future generation of High Energy Physics Experiments
        The electromagnetic noise characterization of the FEE and the compatibility of the different systems are important topics to consider during the experiment upgrades. A new power distribution scheme based on switching power converters is under study and will define a noticeable noise source very close to the FEE detector electronics. The knowledge of the FEE noise issues in previous detectors is an important object to guarantee the design goals and the good functionality of the detector upgrade. This paper shows an overview of the noise susceptibility studies performed in different CMS sub-detectors. The impact of different topologies in the final FEE sensitivity and design recommendations are presented to increase the robustness of the systems to the future challenging power distribution topologies.
        Speaker: Dr Fernando Arteche (Instituto Tecnológico de Aragón)
        Paper
        Poster
      • 114
        Development and Testing of an Advanced CMOS Readout Architecture dedicated to X-rays silicon strip detectors
        An advanced VLSI analog readout architecture, dedicated for X-ray imaging. Critical design issues such as the noise optimization and the shaper implementation technique are addressed and the first test results of a fabricated prototype in a 0.35 μm 3.3 V CMOS process are presented. Important feature of the design is the novel CR-RC2 pulse shaper configuration since in this section, transconductor circuits are used in order to provide a broad range of continuous variable peaking time, programmable gain and adjustable undershoot while still maintaining the noise performance and the required linearity of the specific radiation detection application.
        Speaker: Prof. Stylianos Siskos (Aristotle Univ. of Thessaloniki, Physics Dept., Electronics Lab.,)
        Paper
      • 115
        Development of a fast readout system for DEPFET sensors
        The DEPFET sensor is a favorable technology for use in particle physics experiments. The current system is developed for application in the vertex detector of the planned International Linear Collider (ILC). Besides high spatial resolution, low noise and a low material budget a very high readout speed is required. A new prototype readout system has been built; utilizing a new generation of DEPFET sensors (PXD5) with up to 256x1024 channels, new steering ASICs (called Switcher3), new readout ASICs (called DCD2) and a new FPGA-based high speed PCB. An overview of this system will be given and first measurements will be shown.
        Speaker: Mr Manuel Koch (University of Bonn - Physikalisches Institut)
      • 116
        Digital part of PARISROC: a photomultiplier array readout chip
        PARISROC is the front end ASIC designed to read 16 PMT for neutrino experiments. It’s able to shape, discriminate, convert and readout data in an autonomous mode. The digital part manages each channel independently thanks to 4 modules: top manager, acquisition, conversion and readout. Acquisition is in charge to manage the SCA with a depth of 2 for charge and fine time measurement. Coarse time measurement is made with a 24 bits gray counter. Readout module sends converted data of hit channels to an external system. Top manager controls the start and stop of the 3 others modules. The ASIC will be submitted in June 2008.
        Speaker: Mr FREDERIC DULUCQ (Laboratoire de l Accelerateur Lineaire)
        Paper
        Poster
      • 117
        Distributed Low Voltage System for the FrontEnd electronics of the HADES RPC TOF wall
        This contribution presents the power supply system designed for the frontend electronics of the HADES RPC detector, installed at GSI (Darmstadt, Germany). The system is designed as a distributed architecture and contains custom Low Voltage boards based on DC-DC switching converters to obtain high efficiency and reduce spacing. The switching converters have been conveniently filtered to reduce EMI, obtaining very low output noise. Experimental results prove that the low noise levels achieved at the output of the switching converters behave as good as laboratory power supplies, not producing any worsening in the response of the frontend electronics.
        Speaker: Mr Alejandro Gil-Ortiz (IFIC)
      • 118
        Electronics of LHCb calorimeter monitoring system
        All calorimeter sub-detectors in LHCb, the Scintillator Pad Detector (SPD), the Preshower detector (PS), the Electromagnetic Calorimeter (ECAL) and the Hadron Calorimeter (HCAL) are equipped with the Hamamatsu photomultiplier tubes (PMT) as devices for light to electrical signal conversion. The PMT gain behavior is not stable in a time, due to changes in the load current and due to ageing. The calorimeter light emitting diode (LED) monitoring system has been developed to monitor the PMT gain over time during data taking. Furthermore the system will play an important role during the detector commissioning and during LHC machine stops, in order to perform tests of the PMTs, cables and FE boards and measurements of relative time alignment. The aim of the paper is to describe the LED monitoring system architecture, some technical details of the electronics implementation based on radiation tolerant components and to summarize the system performance.
        Speaker: Dr Anatoli Konoplyannikov (Institute for Theoretical and Experimental Physics (ITEP))
        Paper
      • 119
        Evaluation of high-speed single fiber communication using Wavelength Division Multiplexing.
        There are many reasons for keeping the number of communication fibers in a data acquisition system to a minimum. We are therefore evaluating different schemes for using Wavelength Division Multiplexing (WDM) techniques. WDM is a useful tool for achieving high data bandwidths when up scaling current systems and to allow fiber sharing between multiple data sources. Different strategies such as single fiber single wavelength (SFSW), diplex transceivers and modulation using off board laser sources are investigated. While the primary target is related to the ATLAS upgrade, the work can also have more general applications. Key concepts are cost, size, ruggedness and scalability.
        Speaker: Mr Daniel Eriksson (Department of Physics-Stockholm University)
      • 120
        Fast FPGA-based trigger and data acquisition system for the CERN experiment NA62: architecture and algorithms
        We present the design of the trigger and DAQ system for NA62, with emphasis to the first level of trigger (L0). The L0 level runs on-line and is designed as a segment of the DAQ chain. FPGAs are used to evaluate fast trigger conditions, entirely on the digitized information from read-out electronics. In this way, the whole digitized information from detector is available for triggering and no separate branchs of read-out electronics are necessary. We shall present our design for the L0 architecture, the implementation of trigger conditions on the FPGAs, the hardware we developed and tests.
        Speaker: Ermanno Imbergamo (Univ + INFN)
      • 121
        Fast transient recorder for spectroscopy experiments
        Many experiments in physics with high data rates, short analog signal pulses (40ns), fast rising edges and large dynamic ranges require transient recorders with very high resolution. Additionally double pulses can occur on many spectroscopy experiments, like the COMPASS recoil proton detector. These pulses are recorded and separated by numerical digital processes to extract time and amplitude information and used to create a trigger signal. To meet these challenging requirements the so-called GANDALF transient recorder has been developed with a resolution of 12bit at 1Gsps. Extended with additional memories this module is not only a dead time free readout system but also has huge numerical capabilities provided by the implementation of a Virtex5SXT FPGA to solve challenges for double pulse separation and timing resolution in the sub-nanosecond range.
        Speaker: Mr Florian Herrmann (Fakultaet fuer Physik - Albert-Ludwigs-Universitaet Freiburg)
      • 122
        FPGA Implementation of Optimal Filtering Algorithm for TileCal ROD System
        Traditionally, Optimal Filtering Algorithm has been implemented using general purpose programmable DSP chips. Alternatively, new FPGAs provide a highly adaptable and flexible system to develop this algorithm. TileCal ROD is a multi-channel system, where similar data arrives at very high sampling rates and is subject to simultaneous tasks. It include different FPGAs with high I/O and with parallel structures that provide a benefit at a data analysis. The Optical Multiplexer Board is one of the elements presents in TileCal ROD System. It has Cyclone devices that present an ideal platform for implementing Optimal Filtering Algorithm. Actually this algorithm is performing in the DSPs included at ROD Motherboard. This work presents an alternative to implement Optimal Filtering Algorithm.
        Speaker: Dr Jose Torres (Universidad de Valencia)
        Paper
      • 123
        Grounding, Shielding and Cooling Issues on LHCb electronics at the LHC pit 8.
        The grounding, shielding and cooling issues are important factors in the design and the maintenance of all the electronics systems. Inadequate grounding, shielding or cooling can lead to unreliable operation of the sub-detectors. This paper provides an overview on the LHCb strategy and achievements in the field of grounding, shielding and cooling for the electronics equipments.
        Speaker: Dr Daniel Lacarrere (CERN)
        Paper
        Poster
      • 124
        High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
        Two high-resolution time-interval measuring system implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA and high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.
        Speaker: Dr Salvatore Loffredo (Dipartimento di Fisica, INFN Sezione di Roma Tre and Università di Roma Tre)
        Paper
        Poster
      • 125
        Implementation of the control and supervision of ALICE ZDC positioning systems
        The ALICE Zero Degree Calorimeters (ZDC) have been installed to either side of the LHC IP2 in the machine tunnel next to the dipole magnet D2. The calorimeter modules are mounted on a special table equipped with a mechanism to lower the modules away from the beam orbit during injection and acceleration. During stable operation the modules can be raised individually to be aligned with the beam orbit. The horizontal clearance between ZDC modules and beam pipe will be only about 3 mm. Anti-collision switches are therefore installed to protect the beam pipes against accidental damage. The movement of the calorimeter modules and the protection switches are remote controlled by the ALICE ZDC positioning system.
        Speaker: Mr Detlef Swoboda (CERN)
        paper
      • 126
        Infrastructures and monitoring of the on-line CMS computing center
        This paper describes in detail the infrastructures/installation of the CMS on-line computing center (CMSCC) and its associated monitoring system . In summer 2007, 640 readout Units/builder Units have been deployed along with ~150 servers for DAQ general services. Since summer 2008, ~500 filter units have been added and today, the CMSCC has an on-line processing capability sufficiant for a LV1A trigger rate of 50 kHz. To ensure that these ~1300 servers are performing the tasks we expect from them, a multi-level monitoring system has been put in place. This system is also described in this paper.
        Speaker: Dr Attila RACZ (CERN)
        Paper
      • 127
        Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors
        This work describes a laboratory instrument that was developed to characterize the gate current noise performances of CMOS devices with minimum feature size in the 100 nm span. As a consequence of the reduction of the gate oxide thickness, these devices are affected by a non-negligible gate current due to direct tunneling phenomena. In this paper, the analysis of this noise contribution is particularly aimed at evaluating the resolution limits of readout circuits that will be used in future high energy physics (HEP) experiments. The noise measuring instrument and some of the results of gate current noise characterization will be presented.
        Speaker: Luigi Gaioni (Università di Pavia, I-27100 Pavia, Italy)
        Paper
      • 128
        LLRF electronics for the CNAO synchrotron
        The Italian National Centre for Oncological hAdrontherapy (CNAO) is undergoing its final construction phase in Pavia and will use proton and carbon ion beams to treat patients affected by solid tumors. At the hearth of CNAO is a 78 meters circumference synchrotron, capable of accelerating particle up to 400 MeV/u with a repetition rate of 0.4 Hz. Particle acceleration is done by a unique VITROVAC load RF cavity operating at a frequency between 0.3 and 3MHz and up to 3kV peak amplitude. This paper describes the Low Level RF electronics developed for this synchrotron.
        Speaker: Mr Christophe VESCOVI (LPSC/CNRS/IN2P3/UJF)
      • 129
        Low Power Multi_dynamics Front End for the Optical Module of a neutrino underwater telescope
        A proposal for a new front-end architecture intended to capture signals in the optical module of an underwater neutrino telescope is described. It concentrates on the problem of power consumption, signal reconstruction, charge and time precision. Preliminary test results on a demonstration board are shown.
        Speaker: Dr Domenico Lo Presti (CATANIA UNIVERSITY - PHYSICS DEPARTMENT)
      • 130
        Mezzanine Cards for the EMU CSC System Upgrade at the CMS
        In this paper we discuss two ideas related to the design and application of mezzanine cards in the Endcap Muon (EMU) Cathode Strip Chamber (CSC) electronic system at the CMS experiment at CERN. The first is a proposal to upgrade the FPGA-based mezzanine cards using the most advanced Xilinx Virtex-5 family of FPGA. The second is related to design of a simple and compact mezzanine card with a commercial serializer/deserialzer device and industry standard pluggable optical or copper transceiver module. Such a card could be a basic element of the general purpose gigabit data transmission link.
        Speaker: Mr Mikhail Matveev (Rice University)
        Poster
        proceedings
      • 131
        Noise analysis of Radiation Detector Charge Sensitive Amplifier Architectures.
        In this work, a detailed comparison of four equivalent charge-sensitive, folded-cascode amplifiers in terms of noise performance is presented. A couple of complementary structures, one with a noise-optimised input nMOSFET and the other with a noise-optimised input pMOSFET were designed in 0.35 um CMOS process by Austria MicroSystems (AMS). Another couple of complementary structures consisting of a noise-optimised input npn with a pMOSFET cascode, and the respective structure having a pMOS as input device, were developed in a 0.35 um SiGe BiCMOS process (AMS). The structures' comparison is performed through simulation, after careful selection of the parameters that remain constant in all four variations.
        Speaker: Prof. Stylianos Siskos (Aristotle Univ. of Thessaloniki, Physics Dept., Electronics Lab., Thessaloniki, Greece)
        Paper
      • 132
        Operational Experience With The SCT Optical Links
        The optical links for the SCT have all been installed in ATLAS and are now used for data taking. This talk will review the processes required for the commissioning the links and the tools used to set-up the links and monitor their performance. This allows for an assessment of the current quality of the optical links as well as starting to monitor their long term performance. The methodology for setting up the timing of the TTC links will be described. Lessons learned from the commissioning of the optical links will be discussed.
        Speaker: Dr Anthony Weidberg (Nuclear Physics Laboratory)
      • 133
        Performance of Specific Multi-Mode and Single Mode Passive Optical Components to Co60 Gamma Rays up to SLHC Integrated Doses
        The luminosity upgrade for the LHC (SLHC), will require new inner detectors capable of operating in the harsher SLHC environment. The expected SLHC doses are a factor of four times higher than those assumed for the LHC detectors. An optical readout system is planned for which all on-detector components must be significantly more radiation tolerant than was required for the current LHC detectors. This paper presents first results on radiation tests of all the passive optical components that might be required inside the SLHC tracking detectors. The methodology for this testing will be described, so that meaningful comparisons can be made with data from other groups. Optical components based on 850 nm or 1310 nm were tested. A new more radiation tolerant and faster GRIN fibre than used by the current ATLAS detector was tested to the full SLHC dose. Tests were also done to study the dose rate dependence of the fibre damage. The SM fibre at 1310 nm used by the current CMS detector was also tested up to the SLHC dose. Radiation tolerance tests of fused taper and PLCC splitters and of small form factor connectors for 850 nm and 1310 nm were completed. The facility at the SCK-CEN reactor centre in Belgium was used. The exposures used Co60 gamma sources with dose rates of 15.2 kGy/hr and 1.5 kGy/hr. The results for the GRIN fibre will also be compared with results from the SMU group at even lower dose rates.
        Speaker: Dr B. Todd Huffman (University of Oxford)
      • 134
        PMM2 ASIC : PARISROC
        PARISROC is a complete read out chip in AMS SiGe 0.35m technology for photomultipliers array. It is made to allow triggerless acquisition for next generation neutrino experiments. The ASIC integrates 16 independent channels with variable gain and provides charge and time measurement by a 12-bit ADC and a 24-bits Counter.
        Speaker: Dr Gisele Martin-Chassard (IN2P3/OMEGA-LAL)
        Paper
      • 135
        Power Distribution in a CMS Tracker for SLHC
        In the current CMS tracker power cables constitute a substantial fraction of its dead-material. In an upgraded tracker for an SLHC the current scheme of supplying power independently to each module is unlikely to be tenable due to excessive dead-material. A review of the current ideas for power distribution for a CMS tracker at the SLHC are presented, the experimental methods used to evaluate the performance of different schemes is described and the ongoing tests of different options are outlined.
        Speaker: Dr David Cussans (University of Bristol)
        Paper
        Poster
      • 136
        Radiation Damage of SiGe HBT Technologies at Different Bias Configurations
        SiGe BiCMOS technologies are being proposed for the Front-end readout of the detectors in the middle region of the ATLAS-Upgrade. The radiation hardness of the SiGe bipolar transistors is being assessed for this application through irradiations with different particles. Biasing conditions during irradiation of bipolar transistors or circuits have an influence on the damage and there is a risk of erroneous results. We have performed several irradiation experiments of SiGe devices from IHP in different bias conditions. We have observed a systematic trend in gamma irradiations, showing a smaller damage in transistors irradiated biased compared to shorted or floating terminals. On the other hand, no differences have been observed in neutron irradiations.
        Speaker: Dr Miguel Ullán (CNM-IMB (CSIC), Barcelona)
        Paper
      • 137
        Results on the Perfomance of the CMS Global Calorimeter Trigger for Electrons and Jets
        The CMS Global Calorimeter Trigger (GCT) is the device within the CMS Calorimeter Trigger system which is assigned the tasks of finding and sorting forward-, central- and tau-jet candidates, sorting isolated and non-isolated electron candidates, and reading out all the calorimeter trigger data. The GCT system is modular and uses 1.6 Gbps optical links to concentrate the calorimeter data in eight processing cards which accomplish the algorithm tasks by utilizing Virtex-II-Pro Xilinx FPGAs. The entire GCT system, including both electron- and jet-trigger hardware, has been installed and commissioned in the CMS underground cavern, USC-55. A sophisticated software package has been developed for controlling and configuring the GCT hardware and well as for monitoring the GCT status. Over the past one and a half years the GCT system has undergone detailed testing and its performance is well understood. The GCT design provides buffers at its inputs capable of holding 2048 events; these have been used to inject energy depositions corresponding to electrons and jets in order to test the GCT functionality by comparing its output with that of the GCT emulator. Entire SUSY, Higgs and QCD Monte Carlo background events that have a large number of jets in the final state have been used to validate the GCT performance. The results from all these studies are presented.
        Speaker: Dr Robert Frazier (H.H. Wills Physics Laboratory)
      • 138
        SKIROC : A front-end chip to read out the imaging Silicon-Tungsten calorimeter for ILC
        Integration and low-power consumption of the read-out ASIC for the International Linear Collider (ILC) 82-million-channel W-Si calorimeter must reach an unprecedented level as it will be embedded inside the detector. Uniformity and dynamic range performance has to reach the accuracy to achieve calorimetric measurement. A first step towards this goal has been a 10,000-channel physics prototype of 18*18 cm which is currently in test beam in Fermilab. A new version of a full integrated read out chip (SKIROC) has been designed to equip the technologic prototype to be built for 2009. Based on the running physics prototype ASIC (FLC_PHY3), it embeds most of the required features expected for the final detector. The dynamic range has been improved from 500 to 2000 MIP. An auto-trigger capability has been added allowing built-in zero suppress. The number of channel has been doubled reaching 36 to fit smaller silicon pads and the low-noise charge preamplifier now accepts both AC and DC coupled detectors. After an exhaustive description, the extensive measurement results of that new front-end chip will be presented. The characteristics of the new features such as internal ADC, auto-gain select or self-trigger will be detailed. The results on the technological R&D concurrently conducted on the ultra-thin PCB hosting both the front-end electronic and the silicon detectors will also be described.
        Speaker: Mr Julien Fleury (LAL - Omega)
        Paper
        Poster
      • 139
        SPECS: a Serial Protocol for the Experiment Control System of LHCb
        The LHCb sub-detector electronics requires a configuration bus able to communicate efficiently and reliably over an up to 120-meter line, between a master, located in the counting room which is not exposed to radiation, and up to 32 slaves located on the detector close to electronics boards. The slaves have been developed in order to work properly in radiation exposed environment (up to 40Krad of total dose). The SPECS system is composed of a master board, that hosts 4 SPECS masters, and slaves (mezzanine boards) which provides all the necessary service functions and offers different bus interfaces.
        Speaker: Daniel Charlet (Laboratoire de l''Accelerateur Lineaire (LAL) (IN2P3) (LAL))
      • 140
        Sub-Nanosecond Machine Timing and Frequency Distribution Via Serial Data Links
        FERMI@ELETTRA is a 4th generation light source under construction at Sincrotrone Trieste. It will be operated as a seeded FEL driven by a warm S-band Linac which places very stringent specifications on control of the amplitude and phase of the RF stations. The local clock generation and distribution system at each station will not be based on the phase reference distribution but rather on a separate frequency reference distribution which has significantly less stringent phase stability requirements. This frequency reference will be embedded in the serial data link to each station and has the further advantage of being able to broadcast synchronous machine timing and clocking signals with sub-nanosecond temporal accuracy. This paper describes the design of new RF controls, and specifically the architecture used to distribute the frequency reference along with the precision machine timing and clocking signals.
        Speaker: Tony Rohlev (Sincrotrone Trieste)
        Paper
      • 141
        Testing and calibrating analogue inputs to the ATLAS Level-1 Calorimeter Trigger
        The ATLAS Level-1 Calorimeter trigger is a hardware-based system which aims to identify high-pt objects within an overall latency of 2.5us. It is composed of a Preprocessor system which digitises 7200 analogue input channels, determines the bunch crossing of the interaction, and provides a fine calibration; and two subsequent digital processors. The Preprocessor system needs various channel dependent parameters to be set in order to provide digital signals which are aligned in time and have proper energy calibration. The different techniques which are used to derive these parameters are described along with the quality tests of the analogue input signals. Results from first collision data are expected.
        Speaker: Dr Rainer Stamen (University of Heidelberg)
        Paper
      • 142
        The Alice Pixel Trigger Control and Calibration
        The ALICE Silicon Pixel Detector (SPD) optical data stream includes 1200 Fast-OR signals indicating the presence of at least one pixel hit in each of the detector readout chips. The Pixel Trigger (PIT) extracts the Fast-OR signals from the data lines and processes them to contribute to the Level 0 trigger in the ALICE Central Trigger Processor (CTP). We present here the design, the implementation and the first operational experience of the PIT Control and Calibration system. The PIT Control system includes original hardware and software solutions to implement coordinated operation of the PIT with the various ALICE systems to which it interfaces to.
        Speaker: Cesar Torcato De Matos (University of Minho)
        Paper
      • 143
        The Associative Memory for the Self-Triggered SLIM5 Silicon Telescope
        Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections to be efficient selecting the rare events inside the huge background. We present a fast, high-quality, track-based event selection for the self-triggered SLIM5 silicon telescope. This is an R&D experiment whose innovative trigger will show that high rejection factors and manageable trigger rates can be achieved using fine-granularity, low-material tracking detectors. The system performances will be measured on a test beam, using noisy conditions to simulate high-occupancy . This strategy requires massive computing power to minimize the online execution time of complex tracking algorithms. Affordable latency and rates are provided by a dedicated device, the Associative Memory (AM). The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the AM exploiting parallelism to the maximum level: it compares the event to precalculated “expectations” (pattern matching) at once. This approach reduces to linear the typical exponential complexity of the CPU-based algorithms. The problem is solved by the time data are loaded into the AM devices. We describe the AM-based trigger and its performances.
        Speaker: Francesco Crescioli (Univ. of Pisa + INFN Pisa)
      • 144
        The CMS Low Voltage System
        The power system for the on-detector electronics of the CMS Experiment comprises approximately 12000 low voltage channels, with a total power requirement of 1.1 MVA. The radiation environment inside the CMS experimental cavern combined with an ambient magnetic field reaching up to 1.3 kGauss at the detector periphery severely limit the available choices of low voltage supplies, effectively ruling out the use of commercial off-the-shelf DC power supplies. Typical current requirements at the CMS detector front end range from 1A-30A per channel at voltages ranging between 1.25V and 8V. This requires in turn that the final stage of the low voltage power supply be located on the detector periphery. Power to the CMS front-end electronics is stabilized by a 2 MVA UPS located in a CMS surface building. This UPS isolates the CMS detector from disturbances on the local power grid and provides for 2 minutes of autonomy following a power failure, allowing for an orderly shutdown of detector electronics and controls. This talk will describe the design of the CMS Low Voltage system, review the process of its installation and commissioning, and present the first results of noise measurements performed on the detector.
        Speaker: Dr Sergei Lusin (Fermi National Accelerator Laboratory (FNAL))
        Paper
      • 145
        The Common Infrastructure Control of the Atlas experiment
        ATLAS is the largest particle detector at the new accelerator Large Hadron Collider (LHC), scheduled to start operations in summer 2008 at CERN in Geneva, Switzerland. ATLAS will study proton-proton collisions at the unprecedented energy of 14TeV. In order to guarantee efficient and safe operation of the ATLAS detector, an advanced Detector Control System (DCS) has been implemented. With more than 150 PCs, the DCS is a highly distributed system, hierarchically organized for operating the detector. An important role is played by the Common Infrastructure Control (CIC), supervising the experimental area. The CIC provides monitoring and control for the environment in the cavern and in the counting rooms, all common services like cooling and ventilation, electricity distribution, gas and cryogenic systems. Distributed I/O concentrators, called Embedded Local Monitor Boards (ELMB), have been developed to operate under the special conditions of the experiment such as strong magnetic field and ionizing radiation. They are used for a variety of applications and are geographically distributed over the whole experiment. The communication is handled via the Controller Area Network (CAN) fieldbus using the CANopen protocol. Data is managed by the CIC control station where a commercial Supervisory Control And Data Acquisition (SCADA) package runs. Information and high level control is available to the users by a Finite State Machine (FSM) software running in the control room and information is also available on the web. The technical infrastructure of ATLAS is already continuously supervised during the commissioning phase by the CIC and ensures safe operation.
        Speaker: Mr Olivier Gutzwiller (Conseil Europeen Recherche Nucl. (CERN))
        Paper
        Poster
      • 146
        The Data Acquisition System of the MAGIC-II Telescope
        The MAGIC telescope is the world’s largest gamma ray telescope, designed to look at the light emitted by air shower by Cherenkov effect. It is operating since 2004 at the Roque de Los Muchachos observatory, La Palma, Canary islands. MAGIC-II is the upgrade of the project, consisting of a twin telescope frame with innovative features like new photon detectors to lower the threshold energy further and an ultrafast signal sampling to reduce the effect of the diffuse night sky background. The new acquisition system is based upon a low power analog sampler (Domino Ring Sampler) with frequency ranging from 1.5 to 4.5 GHz and data are digitized with a 12 bit resolution ADC. The analog sampler, originally designed for the MEG experiment, has been successfully tested on site and showed a very good linearity and single photon discrimination capability. Data management are performed by 9U VME digital boards called PULSAR (PULser And Recorder) which handle the data compression and reformatting as well. Every board has 32 analog channels plus auxiliary digital signals for trigger and monitor purposes. For a kHz trigger rate and a 2 GHz frequency sampling, the data throughput can be as high as 100MB/s thus being a challenge for modern data transmission and storage solutions. The data are transferred to PCI memory via Gbit optical links using the CERN S-Link protocol and to the mass storage system. The Data Acquisition system design is described in detail.
        Speaker: Dr Massimiliano Bitossi (INFN PISA)
      • 147
        The Liquid Argon Jet Trigger of the H1 Experiment at HERA
        The Liquid Argon Jet Trigger, installed in the H1 experiment at HERA, implements in 800 ns a real-time cluster algorithm by finding local energy maxima, summing their immediate neighbors, sorting the resulting "jets" by energy, and applying topological conditions. It operated since the year 2006 and drastically reduced the thresholds for triggering on electrons and jets.
        Speaker: Dr Olivier Bob (Max Planck Institute for Physics, Munich)
      • 148
        The TOTEM Roman Pot Motherboard
        The TOTEM Roman Pot Motherboard (RPMB) is the main component of the Roman Pot front-end electronic system. It is mounted on the Roman Pot between detector hybrids and patch panel. The RPMB main objectives are to acquire on-detector data and trigger information from up to 10 hybrids, to perform data conversion form electrical to optical format and to transfer it to the next level of the system. It also distributes the control information to the hybrids and collects different types of information like temperature, pressure and radiation inside the pot. The TOTEM Roman Pot Motherboard, its components and connectivity are presented in this paper.
        Speaker: Mr Gueorgui Antchev (CERN PH-TOT)
        Paper
        Poster
      • 149
        The VFAT production test for the TOTEM experiment.
        VFAT is the front-end ASIC designed for the charge readout of silicon and gas detectors within the TOTEM experiment of the LHC. A stand alone portable Totem Test Platform (TTP) with USB interface has been developed for the systematic testing of the TOTEM hybrids equipped with VFAT chips. This paper is divided into 3 sections; the first describes the hardware features of the TTP, the second describes the software routines for the control and systematic testing of VFATs, the third presents the production test results including yield.
        Speaker: Dr Paul Aspell (CERN)
        Paper
        Poster
    • 20:00
      Conference Dinner
    • Parallel Session A6 - Trigger2
      • 150
        The Sector Collector of the CMS DT Trigger System: Installation and Performance
        Drift Tubes chambers are used for muon detection in the central region of the CMS experiment at LHC. Custom electronics is used for reconstructing muon track segments and for triggering the CMS readout. The trigger Sector Collector modules collect muon segments identified by the on-chamber devices, synchronize the data received from different chambers and convert from LVDS to Optical for transmission to the off-detector electronics. Installation and integration tests were developed for tuning both firmware and hardware of the Sector Collector system: results will be reviewed. The system performance during CMS data taking with cosmic rays and LHC beam (if available) will be discussed.
        Speaker: Dr Riccardo Travaglini (Dipartimento di Fisica-INFN Bologna-Italy)
        Paper
        Slides
      • 151
        The commissioning status and results of ATLAS Level1 Endcap Muon Trigger System
        The ATLAS Level1 endcap muon trigger selects interesting events containing muons with Pt greater than 6GeV/c from 40MHz proton-proton collisions. This system consists of 3,600 Thin Gap Chambers (TGCs) and the total number of readout channels is 320,000. This trigger logic is based on the coincidence between 7 layers of TGCs. All processes are performed on fast electronics within 2.5 micro seconds. To be ready for the first beam scheduled in 2008, we have succeeded in sending trigger signal of cosmic-ray muons with the synchronous operation at 40MHz and a fine signal timing adjustment. We will report on status of the commissioning and results from combined runs with other ATLAS detectors.
        Speaker: Mr Yasuyuki Okumura (Nagoya University)
        Paper
        Slides
      • 152
        Level-3 Calorimeter Resolutions Available for the Level-1 and Level-2 CDF Triggers.
        As the Tevatron luminosity increases more sophisticated selections are required to be efficient in selecting rare events from a very huge background. To cope with this problem, CDF has pushed the level 3 calorimeter algorithm resolutions up to Level 2 and, when possible, even at Level 1, increasing efficiency and, at the same time, keeping under control the rates. This strategy increases the purity of the Level 2 and Level 1 samples, produces free-bandwidth that allows to reduce the thresholds. The global effect is an increase of the signal efficiency on important Tevatron Standard Model Higgs search channels (H -> WW, HZ, HW). The L2 upgrade improves the cluster finding algorithm, the resolution of the Missing Transverse Energy (MET) and the SUM Transverse Energy (SUMET) calculations. The same Level 2 MET and SUMET improved resolution has been made available to the Level 1 system, exploiting the same hardware used for the Level 2 upgrade. The upgrade is based on the Pulsar board [1], a general purpose VME board developed at CDF and already used for upgrading both the Level 2 tracking and the Level 2 global decision crate [2]. The Level 2 upgrade has been designed, built, tested and commissioned in six monthes. It was accepted as the default system for CDF in August 2007. The same Level 2 hardware can be used in such a way to provide the Level 1 colorimeter system of the same MET, SUMET resolution provided to Level 2. While in the upgraded Level 2 system the algorithms are executed in a commercial CPU within the typical Level 2 processing timing of 20 us, in the upgraded Level 1 system, MET and SUMET are calculated by powerful FPGAs[3] within 5 us. The Level 1 upgrade is currently ongoing and in commissioning phase. We describe the CDF Level 2, Level 1 calorimeter upgrades, the architecture and the trigger performances, with particular emphasis on a new calorimeter MET_JET-based trigger performances used for CDF Higgs search.
        Speaker: Virginia Greco
        Paper
        Slides
      • 153
        Commissioning of the ATLAS Level-1 Central Trigger system
        The ATLAS Level-1 Central Trigger (L1CT) consists of the Central Trigger Process (CTP) and the Muon to Central Trigger Processor Interface (MuCTPI). The CTP forms the final Level-1 Accept (L1A) decision based on the information received from the Level-1 Calorimeter Trigger system and from the muon trigger system through the MuCTPI. Additional inputs are provided for the forward detectors, the filled-bunch trigger, and the minimum-bias trigger scintillators. The CTP also receives timing signals from the LHC machine. It fans out the L1A together with timing and control signals to the Local Trigger Processor (LTP) of the sub-detectors. Via the same connections it receives the Busy signal to throttle the Level-1 generation. Upon generation of L1A the L1CT sends trigger summary information to the DAQ and Region-of-Interest to the Level-2 Trigger system. In this contribution we will present an overview of the final L1CT trigger system as it is now installed in the ATLAS experiment and we will describe the current commissioning and integration activity at the experimental site. The system is now continuously used during cosmic-ray runs to exercise the full trigger chain and read-out of sub- detectors. These test are bridging the experiment towards the commissioning phase with protons in the LHC as it is foreseen for this summer. We will discuss in particular the results achieved in operating the system with cosmic-rays and, possibly, the commissioning results with the first proton events in the LHC.
        Speaker: Andrea Messina (Conseil Europeen Recherche Nucl. (CERN)-Unknown-Unknown)
        Paper
        Slides
      • 154
        Modular Trigger Processing - The GCT Muon/Quiet bit System and future applications
        The CMS Global Calorimeter Trigger HCAL Muon and Quiet bit processing function is being implemented with a micro TCA system. This system is reconfigurable in both logical functionality and data flow, allowing great flexibility to meet processing requirements. The system consists of a processing module based on a Xilinx Virtex 5 FPGA and custom backplane based on a Mindspeed crosspoint switch. Initial test results of the processing module will be available, and the overall progress of the design will be presented. In addition, future application of this technology for the SLHC level 1 trigger will be discussed.
        Speaker: Mr Matt Stettler (CERN)
        Paper
        Slides
    • Parallel Session B6 - Programmable Logic, boards, crates and systems
      • 155
        Transmission-Line Readout with Good Time and Space Resolutions for a Planicon MCP-PMT
        Time-of-flight techniques with resolution of a one to several picoseconds would allow the measurement of 4-vectors of relativistic particles at high energy colliders, the association of photons with collision vertices, and the construction of spectrometers with which to study muon cooling without magnetic spectrometers. In order to take advantage of photo-detectors with intrinsic single photo-electron resolutions of tens of picoseconds to build large-area time-of-flight systems, one has to solve the problem of collecting signal over distances large compared to the time resolution while preserving the fast time resolution inherent in the small feature size of the detectors themselves. The solution also has to have a manageable number of electronics channels and low total power. We present here the design of a transmission-line readout for a Photonis Planicon micro-channel plate photomultiplier tube (MCP-PMT) that has these characteristics. The MCP-PMT is characterized by single pulse rise times in the order of 200 ps and transit time spreads (TTS) in the order of 30 ps, and an anode 32 by 32 array of pads (1024 total). The readout is implemented on a Rogers 4350B printed circuit board with 32 parallel 50-ohm transmission lines on 1.6 mm centers, each traversing one row of pads. The board is soldered to the 32 by 32 array; each transmission line being read out on each end. We have simulated the electrical properties of the transmission-line readout board with Hyperlynx and Spice simulators. The simulations predict that the readout transmission-lines can achieve a signal bandwidth of 3.5GHz, which should not significantly degrade the time and spatial resolutions intrinsic to the MCP-PMT signals. Results from the simulation and tests will be presented.
        Speaker: Fukun Tang (Enrico Fermi Institute - University of Chicago)
        Paper
        Slides
      • 156
        Incremental Firmware Development and Partial Reconfiguration in the Xilinx Virtex-5
        The size and complexity of the latest generations of FPGAs has increased dramatically. This in turn means that the time taken to develop and build even small firmware projects is increasing exponentially. Pre-constrained logic placement and routing is becoming critically important for the use of specialized components in the FPGA such as serial link interfaces. This necessitates significant changes from 'normal' firmware tool flows in order to effectively develop systems based on these devices. In this paper we discuss several methods for improving turnaround speed and design safety, including: pre-placed and pre-routed hard macros / RPMs, pre-synthesised black-box netlists, and incremental synthesis, place and route. Possible methods of dynamic partial reconfiguration are also discussed in this context.
        Speaker: Dr John Jones (Princeton University)
        Paper
        Slides
      • 157
        The TOTEM T1 detector electronic system
        Totem is an experiment located at CERN and devoted to the measurement of the proton-proton elastic and total cross section at LHC. TOTEM and CMS foresee a program of common measurements on diffractive physics. This presentation will be focused on the design of T1 detector, devoted to the measurement of the inelastic rate, made of Cathod Strip Chambers. We will present the complete electronic readout chain of the Cathode Strip Chambers: the anode and cathode front-end boards, the readout-control card and the trigger unit. Key features of this system are high radiation tolerance and data path, slow control, fast command and trigger compliant with the CMS standards.
        Speaker: Dr Saverio Minutoli (INFN - Genova)
        Paper
        Slides
    • Plenary Session 7 - CLOSE OUT
    • 13:00
      Lunch
    • TUTORIAL - Designing Printed Circuit Boards Not To Fail
      • 158
        Designing Printed Circuit Boards Not To Fail (1)
        1) Circuit boards fail primarily for mechanical and electro-chemical reasons. 2) Failure mechanisms in circuit boards. a) Vibration (mechanical fatigue). b) Mechanical shock (high stress). c) Thermal fatigue (thermally induced fatigue). d) Humidity effects (diffusion of water vapor). e) Condensing moisture effects (electromigration and dendritic growth). 3) These failure mechanisms represent stresses that produce cumulative damage effects that lead to loss of product life over time. 4) “Time-to-failure as a function of the stress” can be modeled as a stress-life relationship on log-log paper. This will later allow us to produce equivalent damage accelerated tests. 5) What is design margin? a) Stress-Strength interference. b) Design margin is also easily portrayed on the life-stress relationship graph. 6) We need design margin for each failure mechanism relative to the damage it will see in its intended lifetime. a) The intended lifetime is defined as the severe use application. 7) How much margin is enough? a) Where does the 3X concept come from? 8) What is “Damage in its intended lifetime” and how do we quantify this damage. a) The severe use situation as a function of the normal use – the other 3X concept. 9) Design process to insure that we have adequate margin against a lifetime of damage for the severe use situation. a) Design equations for thermal fatigue. (example worked in class) b) Design equations for vibration. (example worked in class) c) Design equations for humidity. (example worked in class) d) Design solutions for condensing moisture. (examples shown) 10) Summary of test methods for weakness discovery and design margin evaluation
        Speaker: Mr Larry G. Edson (Consultant)
    • 15:45
      Break
    • TUTORIAL - Designing Printed Circuit Boards Not To Fail
      • 16:15
        [154] Designing Printed Circuit Boards Not To Fail (2)