Speaker
Mr
Marc Fossion
(ThalesAleniaSpace)
Description
Thales Alenia Space is engaged in the development of a radiation hardened mixed-mode circuit: the DPC (digital programmable controller). This device is a major breakthrough in the availability of radiation hardened highly integrated micro-controller.
The construction of the DPC is the result of 4 party project involving Imec, ICsense & Thales Alenia Space under an ESA development. This component uses the Imec RHBD DARE on UMC 0.18µ library and analog IP designed full custom by ICsense. The effective performance characterization of the DPC is currently evaluated in Thales Alenia Space laboratory.
The DPC is an essential building block for the development of intelligent RTU and other (power) distribution units in LEO & GEO satellites. Its large set of communication interface makes it usable in a broad range of applications such as scientific payload control, motors, actuators, battery management, power management … wherever a decentralized control makes the overall solution more efficient.
The presentation covers the key features of the DPC that have been made possible thanks to some extensions of the DARE library such as DPRAM, IO and clock gating. The analog functions such as ADC, DAC, PLL & band gap have been designed such as to minimize the amount of external components needed around DPC (target being a system on chip). The E2prom containing the hardware configuration bitstream and the firmware remains, for this 1st generation, still an external device. Extreme care was taken to SET hardening of the critical analog functions: ICsense having developed automated & systematic charge injection verifications.
First tests results will be presented together with the roadmap to complete the evaluation for space use and the path to deliver flight models.
**Project organisation**
Imec not only has provided the RHBD DARE on UMC 0.18µ library, but also extended it with additional features. Dual port memories are being used to transparently perform memory scrubbing in a seamless manner for the processing unit. The DPC embeds 95Kbytes of memory split over several banks. Clock gating cells have been also added. As the DPC embeds a large range of features, power consumption may become an issue if all of them would be active simultaneously. At boot time, a hardware configuration is loaded in the circuit to only deliver clock toward functions relevant to the target application.
Imec also performed top level layout integrating digital netlist & analog macros, performing DRC to check for compliance to particular radiation hardening rules and finally the interface with UMC foundry.
ICsense has designed a large set of analog IP blocks which are included on chip. Concerning IO offered to the user, there are 4 analog to digital converters 13bits-1MSps with input multiplexing functions. There are also 3 current steering DAC each 12bits-50kSps / 8 bits-1MSps. As supporting function the DPC also includes an on-chip 100kHz RC oscillator for applications that do not require high precision frequency reference. This frequency reference is internally multiplied with a PLL delivering the internal master clock of the circuit. All these function are obviously supported by an on-chip bandgap. A set of internal low-drop voltage regulators converts the incoming 3.3V into +1.8Vdc to supply the digital core and to deliver “noise-less” supply to critical analog functions.
This extensive set of analog function makes DPC a rather standalone system-on-chip (exception being for now the external E2prom).
Besides classical RHBD rules such a guard rings (Latchup) & margins for Vt shifts (dose up to 100krad), ICsense has developed an powerful set of extension on top of (Cadence/Mentor) simulation tools to perform systematic charge injection verifications on each nodes of the circuit. ICsense has completed the design, layout & verifications. The 2 analog macros were delivered to Imec for integration into the final chip layout.
Thales Alenia Space Belgium has developed the RTL code to glue up all IP: the 16bits OpenMSP430 processor, mil-1553b, UART, CAN interfaces, memories, multipliers... On top of the classical simulation at RTL, the DPC has been extensively validated on 2 FPGA platforms. The first one was used to validate all interaction modes foreseen in the DPC feature list. The second one was to integrate the DPC with its software development environment.
Challenge for such a complex mix-mode design resides into the verification of interfaces between analog macros and digital functions. This problem was tackled by the exchange of Wreal models simulating the behavior of analog functions to be used in digital simulations. In the other way, stubs of RTL code have been delivered to simulate analog functions with their interface to digital functions.
Foundry was done by UMC & packaging has taken place at HCM. Wafer probe & package testing used facilities of µTest. The component is now back into the labs & alive: tests ongoing.
Primary authors
Mr
Alain Van Esbeen
(ThalesAleniaSpace)
Mr
Marc Fossion
(ThalesAleniaSpace)
Co-authors
Mr
Claudio Monteleone
(ESA)
Mr
Eldert Geukens
(ICsense)
Mr
Richard Jansen
(ESA)
Mr
Steven Redant
(IMEC)
Mr
Yves Geerts
(ICsense)
