AMICSA 2014 - Fifth International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications

29 Jun 2014, 08:30 → 1 Jul 2014, 18:05 Europe/Zurich

503/1-001 - Council Chamber (CERN)

Boris Glass (European Space Agency), Evelyne Dho (CERN), Francis Anghinolfi (CERN)

The purpose of AMICSA 2014, organised in collaboration with ESA and CERN, is to provide an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

Workshop Topics:

 

• Radiation Effects on Analog and Mixed-Signal ICs,
• Methodologies for Radiation Hardening on Analogue Circuits at Cell Level, Circuit Level, and System Design Level,
• Radiation Hardened Technologies for Analog ICs,
• Radiation Tests of Analog and Mixed-Signal ICs,
• Qualifying and Quantifying Radiation Hardness of Analog Circuits,
• Space Applications for Analog and Mixed-Signal ASICs,
• Analog Intellectual Property and Reusability of Analog Circuits in Space,
• In-Orbit Experiences and Flight Heritage of Analog and Mixed-Signal ICs,
• Needs and Requirements for Analog and Mixed-Signal ICs in Future Space Missions.

 

AMICSA 2014 is organized with support from:

 

 

Practical Information Vademecum_Local_20June_1600.pdf

Proceedings AMICSA Proceedings 2014.pdf

Sunday, 29 June

08:30 → 17:30 Free Time

08:30 → 17:30 Social Programme: Full day excursion to the Vineyards of Pays de Lauvaux and Boat Cruise on Lake Geneva (optional - booking required!)

08:30 CERN Bus / Departure 08:30

Bus departure at CERN

10:00 Vineyards of Pays de Lavaux

Departure of the Lavaux Express train for a tour of the vineyards of Pays de Lavaux

10:30 Wine Tasting

Wine degustation at a local wine cellar

11:30 Return to Cully

Return to Cully by train through the vineyards

12:00 Bus transfer

Continuation to Lausanne (20’) by bus

12:30 Gourmet Cruise

Gourmet Cruise on La Suisse via St-Gingolph, Le Bouveret, Villeneuve, Chillon Castle, Montreux, Vevey, Lavaux

15:20 Boat return / Bus transfer / Arrival at CERN: 17:30

Monday, 30 June

09:00 → 09:30 Opening of the Workshop: Welcome address by Sergio Bertolucci, Director for Research and Computing at CERN

slides

• AMICSA_background.pdf
• Introduction_FA_CERN.pdf
• Introduction_FA_CERN.pptx

09:30 → 10:30 Need and Requirements for Radiation Hardened Analogue and Mixed-Signal ICs

Convener: Boris Glass (European Space Agency)

09:30 Strategy for Radiation Tolerance Assurance of the A&T Electronic Equipment

The radiation environment encountered at high-energy accelerators differs from the environment relevant for space applications. The mixed field expected at modern accelerators is composed of charged and neutral hadrons (protons, pions, kaons and neutrons), photons, electrons and muons, ranging from very low (thermal) energies up to the TeV range. This complex field is due to particles generated by the primary particle collisions in the experimental areas, distributed beam losses around the machine, and the beam interacting with the residual gas inside the beam pipe. Electronic components and systems exposed to a mixed radiation field will experience at once all three different types of radiation damages: Single Event Effects (SEEs), damage from Total Ionizing Dose (TID) and Displacement Damage (DD), where in all cases, not only the particle type, but also the respective energy distribution are to be considered. One important example of the latter are latch-up errors (possibly destructive) where in the context of accelerator environment their cross section can still increase until energies in the GeV range, especially if high-Z materials are present near the device's sensitive region. In addition, for some devices the impact of thermal neutrons is not to be neglected; and when it comes to dose, pure gamma test measurements are partly not fully representative. For the CERN accelerator sector, the control and the functioning of the Large Hadron Collider (LHC) requires many systems and equipment partly to be installed in radiation areas, such as power converters providing up to 13 kA current to the super conducting magnets, safety and monitoring electronics and actuators for discharging the superconducting coils, pumps for creating the required vacuum conditions in the beam pipe, in the magnets, and in the helium distribution line, cryogenic systems to reach the temperature of 4K, and many others. Moreover, depending on the functionality, each system is replicated 10, 100 or 1000 times along the LHC and its injections lines. Within these constraints, the conception of full custom solutions down to the component level is often not possible and must be adopted according to each individual design limitations, defined by the electrical specifications on the one side and the harsh radiation environment on the other. Depending on the latter, in the context of accelerators, an equipment can thus be either a fully commercial system, or a custom development, based on hardened or qualified electronic components, or a mix of the two solutions. Therefore, all exposed electronic systems have to be qualified for their radiation tolerance. The latter has to include a failure analysis and an estimation of the respective impact on accelerator operation. In this context, the device degradation due to cumulative effects, or its functional limitations due to single event failures, is not a limitation by itself, but must be quantified. In terms of respective design acceptance criteria, the performance degradation must not prevent the proper use of the component or the system up to its defined (and qualified) TID and DD targets, as well as the rate of SEE must remain sufficiently low in order to cause only a limited (and acceptable) number of stops of the accelerator, while also keeping as short as possible the consequent machine downtime. Combining all accelerator operation, control and monitoring systems, the R2E project aims for an accelerator operation with a radiation induced ‘Mean-Time Between Failures’ (MTBF) greater than or equal to one week for nominal, ultimate and later high-luminosity operation conditions, therefore finally assuming a peak luminosity of ~5×1034 cm-2s-1 allowing for an annual integrated luminosity of more than 200 fb-1. In order to keep the overall failure rate under control and to reach the goal defined by the MTBF target, one requires a long-term radiation test and qualification strategy trimmed to the needs of the accelerator radiation environment and its applications. Further detailing the above listed constraints and requirements, this paper will present the criteria for choosing radiation test facilities, both standard facilities as well as a new CERN-based one (CHARM), the test strategy and procedure, with flow charts of the radiation tests to be performed, taking into account the type of the equipment, its individual list of required components, as well as the radiation levels of the area where it will be installed. The high radiation environment encountered at the CERN accelerator, the large number of electronic systems and components, as well as the actual impact of radiation induced failures on the overall accelerator operation, strongly differ from the environment and systems usually relevant for space applications. Additional constraints, but in some cases also simplifications, which have to and can be considered with respect to the test and monitoring standards, are respectively summarized.

Speaker: Dr Giovanni Spiezia (CERN, EN/STI on behalf of the RADWG)

Paper AMICSA2014_AT_rat-tol-strategy_v2.pdf

Slides AMICSA2014_37_Spiezia_slides.pdf

09:50 Creating and Updating Standards for New Analog and Mixed-Signal ICs for Space Missions

On December 20, 2013, the Defense Logistics Agency (DLA) released revision K of microcircuit specification, MIL-PRF-38535. This document revision is significant because it updates existing requirements and creates requirements for new analog and mixed-signal integrated circuits (ICs) including those that are built as flip-chips and with columns attached. It also introduces and enables Class Y, a new category of microcircuits for space. Development of Class Y was a NASA-led initiative for the space community to infuse new technology into military/space standards. With the availability of analog-to-digital (A/D) and digital-to-analog (D/A) converters operating in gigahertz (GHz) frequencies, the screening and qualification of such microcircuits is being reviewed by the industry and government users with the goal of clarifying and adding to the existing requirements. Lastly, a summary will be given of radiation characteristics of analog ICs. These single event and total dose radiation characteristics will be presented at the next Nuclear and Space Radiation Effects Conference (NSREC).

Speaker: Mr Shri Agarwal (NASA/JPL-CalTech)

Slides AMICSA2014_01_Agarwal_slides.pdf

10:10 Assessment of Mixed Signal Technology

In 2013, within the ECI (European Component Initiative) program of the European Space Agency, the activity “Assessment and characterization of Mixed Signal Technology” has been initiated. In this paper the activities performed for the assessment and selection of an European mixed signal technology suitable for the development of ASICs for space applications will be described. In order to drive the assessment and selection process three different surveys have been carried out. The main results will be presented in this paper. In the first survey a comparative assessment, the availability of several existing European mixed signal technologies has been performed. The assessment focused on the availability (access, licensing, condition for use, process lifetime, process options, supported tool chain, etc.), environment supported (voltage and temperature range, radiation tolerance, ESD and EMC levels, etc.), quality features (wafer thickness, yield, FIT, PID, failure analysis support, process stability, etc. ), analogue (Spice model accuracy, devices primitives availability, simulators model supported, etc.) and digital (gate density, power consumption, clock frequency, supply voltage range, leakage current, cell libraries, model accuracy, supported tool chain, sign-off, etc.) performances. In the second survey, inputs covering the needs for mixed-signal ASICs from the space community and the Agency's planned missions has been collected. In last survey, information about the existing rad hard libraries and design kits in terms of primitive devices, SEEs, TID and reliability performances have been collected. Six European foundries have been contacted: Atmel, Austria Micro Systems (AMS), IHP Microelectronics, ON Semiconductor, Telefunken Semiconductor and XFAB; the data obtained from a total of 18 technology processes have been collected and analysed. Based on the review of the data obtained by the collected questionnaires and by consideration that multiple mixed signal ESA and national Space Agencies activities are currently on-going on several technologies, the CMOS High Voltage 180nm process with NVM option by XFAB has been chosen for further characterization in phase 2. The work will consist in the design of a test vehicle containing primitive devices and simple circuits. The characterization will consist of I-V and C-V curve extraction, end of life (EOL) test, Total Ionization Dose (TID) test, Single Event Transient (SET) evaluation in term of pulse width and charge injected and it will be aimed to analyze the reliability and radiation test results. The final objective is to extract electrical basic analogue device models and to incorporate those into the design-kit.

Speaker: Franco Bigongiari (SITAEL S.p.A.)

Paper AMICSA2014_20_Bigongiari_paper.pdf

Slides AMICSA2014_20_Bigongiari_slides.pdf

10:30 → 10:50 Coffee Break

10:50 → 11:50 Applications for Radiation Hardened Analogue and Mixed-Signal ASICs: Instrumentation Front-End

Convener: Boris Glass (European Space Agency)

10:50 High performance analog Front End ASIC for interfacing with a Si Drift Detector and the control electronics

In the frame of the LOFT (Large Observatory For x-ray Timing) program, IRAP, CNES and Dolphin Integration have collaborated to develop a high performance ASIC (SIRIUS2) for interfacing Silicon Drift Detectors (SDDs) with the digital back-end LOFT was candidate X-ray mission for the M3 slot of the Cosmic Vision program of the European Space Agency. It will be proposed again for the M4 mission. LOFT is designed to study the neutron star structure and equation of state of ultra-dense matter and to explore the conditions of strong-field gravity. The primary enabling technology for the Large Area Detector (LAD) is the SDDs developed for the Inner Tracking System in the ALICE experiment of the Large Hadron Collider at CERN, by scientific institute INFN Trieste, Italy. The project targets a 10 m² detector array for 2 to 80 keV Xrays detection at high sensitivity (50 – 200 eV) and good energy resolution (limited by electronic noise, itself limited by EOL detector leakage current) with a dead time << 1% at 1 Crab. Such a system will require 500 k to 600 k SDD detectors managed by 35 k to 40 k ASICs. The collaboration among IRAP, CNES and Dolphin Integration targeted these ASICs interfacing the SDDs and the digital back end on the satellite. SIRIUS2 embeds 16 Analog Front Ends (AFEs,) a 12-bit ADC for digitization, DACs for the generation of the threshold for the minimum detectable event, low noise comparators, multipliers and the full digital interface used to control the AFEs and to read the measures. The ASIC was developed using the 180nm mixed technology of TSMC. The harder performances of SIRIUS2 are the energy resolution of 200eV @ 6keV (requiring a very high performance in term of noise corresponding to an ENC of 17 electrons end of life of the SDD), the very low power consumption (lower than 650 µW/channel) and a full scale higher than 22200 electrons. In term of analog design, since the SDD deliver current pulses of low intensity and short duration, the AFE uses an integrator to accumulate the corresponding charge in a capacitor to deliver a voltage output. This structure is called a charge preamplifier, and will be noted CPA here below. In order to add gain and improve signal to noise ratio, the CPA is usually followed by a pulse shaper, working as a matched filter. The output of the CPA plus the shaper is a voltage pulse. Depending on the application, this pulse is either compared to a threshold and sent to an event counter, or sampled and digitized. In order to capture the energy of the Xray events, it is required to detect the pulse maximum and hold the voltage by a Peak and Hold, or P&H here below. Critical performances have been analyzed and quantified. Noise contributions have been estimated and rated. It has been highlighted that important characteristics such as noise, gain, speed, power, area have conflicting requirements and that some trade-offs must be carefully balanced. The resulting formulas will be presented, in parallel to simulations, in order to highlight the technical solutions that have been chosen for LOFT project requirements. The CPA has been designed using switched reset structure based on a gain capacitor of 75 fF. This offers a good balance between preamplifier gain and dead time requirements, while keeping transient behavior of pulse shaper within acceptable limits. Instead of generating a tiny continuous leakage, the capacitor is regularly shorted for a small time (after detection, when leakage current has generated an excessive offset at CPA output). This solution is the best in term of noise with a drawback link to the dead time due to the reset. The noise performance of around 20 ENC at tau of 2 µs, for a dead time lower than 0.7 % meets the initial specifications. For the SHAPER the best trade off comes with CR-RC² topology. Higher the orders lower the ENC. But global optimization requires significant gain in the shaper. Higher order filters (CR²-RC2 or CR-RC3) have lower peak gain. Hence it is necessary to boost resistors ratios, severely loading the CPA or generating higher shaper noise. Simulations have confirmed that total signal to noise ratio was not improved by higher order shapers. For the P&H, a derivation-based peak detector followed by a switched capacitor hold cell will feed the analog to digital converter. The measurement with the SDD have been done at room temperature (≈25°) showing a best value obtained in term of noise of 24.5 e- rms with shaping time 4 us. The gain linearity is very good and the gain is stable over temperature range. The power consumption achieved is lower than 580 µW per channel at room temperature.

Speaker: Andrea Bonzo (Dolphin Integration)

Paper AMICSA2014_DolphinIntegration_1.1.pdf

Slides AMICSA2014_18_Bonzo_slides.pdf

11:10 A radiation-hardened and low flicker noise ASIC preamplifier designed in CMOS technology for the ultra-sensitive ESA JUICE search coil magnetometer

Important space scientific missions such as ESA CLUSTER (2000), NASA THEMIS (2007), NASA MMS (2014), ESA/JAXA BepiColombo (2016) and ESA JUICE (2024) have and will incorporate an ultra-sensitive three-axis Search Coil Magnetometer (SCM) to measure the magnetic field vector. Over the years, the instrument, which is designed by the LPP/CNRS, has become a reliable and essential device due to the in situ demonstrated performances in terms of high magnetic resolution, robustness, low power consumption and its ease of implementation. The SCM operates in low-frequencies from 0.1 Hz to a few dozen kHz. Therefore, in order to achieve a femtoTesla (fT/sqrt(Hz)) sensitivity (noise floor), the equivalent input noise of the readout electronics must be lower than some nV/sqrt(Hz). Here, we are particularly confronted to the flicker noise (1/f). The electronics’ power consumption is to be considered during the design flow since this is a crucial aspect in space applications, among other specifications, for the instrument’s lifetime. Furthermore, related effects to cumulative radiation dose, heavy ions and temperature should not impact the readout electronics specifications and therefore the SCM sensitivity. In this paper, we will introduce the principle of the designed SCM for JUICE (JUpiter ICy moons Explorer) which operates in the frequency range 0.1 Hz – 20 kHz. The SCM should provide a 4 fT @5kHz sensitivity (noise floor). The mission’s environment requires an operating temperature of -150 °C and a total ionizing dose of 300 krads (under shielding). To meet those constraints, an application-specification-integrated-circuit (ASIC) designed in 0.35µm CMOS technology is proposed. It consists of a low flicker noise preamplifier. The interest in a monolithic integration of the readout electronics is explained. An analytic study of MOSFET transistor noise contribution was done to allow the considerable reduction of the flicker noise (1/f) and to achieve, thanks to an appropriate transistors dimensioning, an input equivalent noise of 4 nV/sqrt(Hz) and a current noise of 20 fA/ sqrt(Hz) at 10Hz. The chip was exposed to a 300 krads of Colbalt-60 total ionizing dose (TID) and tested in nitrogen temperature (77 °K). Measured noise and gain variations of the preamplifier do not affect the SCM sensitivity. The ASIC power consumption is 16 mW, which is interesting if compared to previous adopted electronics based on discreet components. The ASIC radiation-hardiness is insured by enclosed-gate layout transistors and guard-rings around each device. In the second section of the paper, we will discuss the new ASIC design, which will include, in addition to the low noise preamplifier, a supply voltage regulator and a band-gap voltage reference. The interest of those new functions is to improve the insensitivity of the supply voltage and the biasing in a wide temperature range, which starts at 77°K.

Speaker: Amine Rhouni (Laboratory of Plasmas Physics (LPP/CNRS))

Slides AMICSA2014_05_Rhouni_slides.pdf

11:30 Radiation hardness tests of the CLARO-CMOS chip: a fast and low power front-end ASIC for single-photon counting in AMS 0.35 micron CMOS technology

The CLARO-CMOS is a prototype ASIC primarily designed for single-photon counting with multi-anode photomultipliers (Ma-PMTs). The chip features 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption in the order of 1 mW per channel. It was developed in the framework of the LHCb RICH detectors upgrade at CERN, but also found application in the readout of Silicon Photo-Multipliers (SiPMs) and microchannel plates. The prototype, realized in AMS 0.35 micron CMOS technology, has four channels, each made of a charge amplifier with settable gain (3 bits) and a comparator with settable threshold (5 bits) that allow tuning the response of the chip to the gain spread of the Ma-PMT pixels. The threshold can be set just above noise to allow an efficient single-photon counting with vacuum photomultipliers. In the readout of SiPMs, the threshold can be set above the single photon signals, allowing to count events with two or more photoelectrons with high efficiency and good separation of the photoelectron peaks. The CLARO-CMOS chip was fully characterized on the test bench. The chip was coupled to a Hamamatsu R11265 Ma-PMT, the baseline photon detector for the LHCb RICH upgrade, and was found able to read-out single-photon signals up to the maximum average rate expected in the LHCb RICH (~10 MHz) with a low power consumption (~1 mW) and a negligible crosstalk between pixels. In the LHCb RICH environment, over ten years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2, the ASIC must withstand a total fluence of about 6x10^12 1 MeV n_eq/cm^2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long-term stability of the electronics front-end. We present results of multi-step irradiation tests with neutrons up to the fluence of 10^14 1 MeV n_eq/cm^2, with protons up to the dose of 8 Mrad and with X-rays up to the dose of 8 Mrad. During irradiation, cumulative effects on the performance of the analog parts of the chip and single event effects (SEE) were evaluated. The chips were biased continuously and the chip threshold voltages were measured regularly, in order to detect possible single event upsets (SEUs) affecting the threshold DAC settings. Power consumption was also monitored online, and an additional circuit provided protection against Single Event Latchup (SEL). S-curves were measured before and after each irradiation step, to follow the evolution of counting efficiency, threshold shifts and noise during the irradiation.

Speaker: Lorenzo Cassina (Universita & INFN, Milano-Bicocca (IT))

Paper AMICSA2014_21_Cassina_paper.pdf

Slides AMICSA2014_21_Cassina_slides.pdf

11:50 → 12:30 Radiation Hardened Technology for Mixed-Signal IC: (1/3)

Convener: Boris Glass (European Space Agency)

11:50 SEE Characterization of a Magnetometer Front-End ASIC using a RHBD Digital Library in AMS 0.35um CMOS

A radiation-hardened-by-design (RHBD) digital library, developed for the Austria Microsystems (AMS) 0.35um CMOS technology has been applied in a mixed-signal ASIC that operates as a multi-channel data acquisition system for magnetometers using anisotropic magneto-resistances (AMR). The circuit has been tested in the Heavy-Ion facilities of the Université Catholique de Louvain-la-Neuve (HIF-UCL). The experimental results demonstrate a LET threshold of 22.5 MeV·cm2/mg and absence of latchup up to 81.8 MeV·cm2/mg. SEE performance of the A/D converters has also been measured. This radiation-tolerant performance is obtained at the cost of a penalty in area and power with respect to the unhardened technology.

Speaker: Mr Juan Ramos-Martos (Instituto de Microelectrónica de Sevilla)

Paper AMICSA2014_03_Ramos_paper.pdf

Slides AMICSA2014_03_Ramos_slides.pdf

12:10 Mixed-Signal Design Methodology for Various Radiation Environments with Applications to a 0.35 μm, 65 V Quadruple-Well BCD Technology

There is a need for high voltage (>5V <100V) mixed-signal integrated circuits (ICs) in a variety of applications having ionizing radiation environments, such as satellite/space, medical diagnostic imaging, nuclear power control & monitoring, and radiation oncology therapy. In some of these environments, the ionizing radiation includes ions (space, proton therapy) while in others, there the ionizing electromagnetic radiation is accompanied by neutrons (nuclear power, radiation therapy). Designing to the worst possible radiation environment can impose severe design limitations that result in higher power, poorer performance, and higher cost than is really necessary for the intended application. We discuss a unified design flow where different radiation environments are accommodated (but not over-accommodated) by the use of distinct sets of design rules, cell libraries, and design tools. The process starts with technology selection and the design and fabrication of a technology characterization vehicle (TCV). The TCV contains at least one (but usually several) instantiations of each active and passive device that are intended to be used by the designers. The fabricated TCV is packaged and electrical test data collected for each device type, e.g. Id-Vg and Id-Vd curves for MOS transistors of various channel lengths (L) and widths (W). Devices are then irradiated using either x-rays or gamma rays to a give total ionizing dose (TID) level, and the same electrical data immediately collected after irradiation. For the first time Id-Vg data is measured for a 65 V NLDMOS in a 0.35 μm quadruple-well bipolar-CMOS-DMOS (BCD) technology for TID levels of 0, 50, 100, and 300 krad(Si), along with the minimum, average, and maximum threshold voltage shift from the population of devices irradiated as a function of TID. This type of data is used to generate compact transistor models that can be used in design simulations for various TID levels. Heavy ion data on these same transistors is used to define the safe operating area (SOA) for use in a space environment. For lower voltage transistors that would be used in the digital portion of a mixed-signal IC, a similar procedure is followed to generate models. In the final paper, we will present TID and single event effects data, for the first time, for 40V and 65V NLDMOS and PLDMOS devices fabricated in a 0.35 μm quadruple-well, 4LM BCD technology, showing SOA, SEL, and calculated ASET rates for select analog cells. Sequential digital cells are designed to meet the single event upset (SEU) requirements of the given application environment. The SEU rate is predicted a-priori by the use of two proprietary design tools, Qsim and SETsim, that were described previously [1]. The SEU rate is then validated by irradiating the TCV containing such cells, typically configured in large memory arrays, with heavy ions and/or protons as appropriate at various values of linear energy transfer (LET) up to ~110 MeV cm2/mg. Several, distinct libraries are then created, each having a TID and single event latch-up (SEL) rating for each cell, a digital single event transient (DSET) for each non-sequential cell, and an SEU rating for each sequential cell. In this way, each of the distinct libraries has an overall rating for radiation environment. Neutron testing is also performed for cells to validate their use in nuclear reactor environments. Analog/Mixed-Signal cells are designed to meet certain recovery times for analog SET (ASET). An analog-to-digital converter (ADC) might have a design target of ASETs having duration of less than two sample clocks for an LET < 40 MeV cm2/mg. Comparators may be rated by the on-set LET that causes a false reading when the input is within, e.g. 10mV of the trip-point, etc. Using the a-priori rating system (with validation by TCV testing), completed mixed-signal libraries are formed and labeled as to their possible radiation environments. The program manager and product development team select the proper mixed-signal library based upon the specification for the mixed-signal IC. Verification that the expected radiation response will be achieved is accomplished using commercial and proprietary simulation tools, and validated by performing radiation testing on the prototype silicon. Several examples of products will be shown in the final paper. [1] D.B. Kerwin, A. Wilson, Y. Lotfi, K. Merkel, and A. Zanchi, “MIXED-SIGNAL DESIGN METHODOLOGY USING A PRIORI SINGLE EVENT TRANSIENT RATE ESTIMATES”, 4th International Workshop on Analog and Mixed Signal Integrated Circuits for Space Applications (AMICSA 2012), 26 - 28 August 2012 ESA/ESTEC, Noordwijk, The Netherlands.

Speaker: Mr David Kerwin (Aeroflex)

Paper AMICSA2014_31_Kerwin_paper.pdf

Slides AMICSA2014_31_Kerwin_slides.pdf

12:30 → 14:00 Lunch

12:30 → 14:00 Social Programme: Atlas Underground Visit

12:30 Group 1

13:15 Group 2

14:00 → 14:40 Radiation Hardened Technology for Mixed-Signal IC: (2/3)

Convener: Richard Jansen (ESA)

14:00 NEW ID MOS PDK for SPACE APPLICATIONS

Two years ago, ID MOS had the first demand to develop mixed-signal ASIC for Space applications. After having a look to the existing PDKs, we discovered that there was still no full Space PDK available, especially with regard to device models. ID MOS decided to develop its own PDK, for the low space voltage applications. This PDK had to provide hardened components to reach the specified radiation tolerance (TID : 100krad, SEL : LET 80,72Mev.cm²/mg). To reach this target we, first, chose a technology, developed our own test chip including different modules based on new ELT transistor drawings, fabricate the circuit, define the assembly and the electrical test. Then for the NEOSAT project, we received the same demand for High Voltage circuits. We chose the same technology XH035 from XFAB complemented with different modules allowing the integration of High Voltage ELT transistors (up to 90V). We propose to present for the radiation hardened XH035 technology the baseline technology test chips and radiation test results. Finally the current state of the ID MOS solution is presented for Space mixed Analog/Digital ASICs, based on the XFAB XH035µm technology.

Speaker: Mr Paul-Emile Latimier (ID MOS)

Paper AMICSA2014_IDMOS_LVDK_v4.pdf

Slides AMICSA2014_04_Latimier_slides.pdf

14:20 Radiation-hardened high-voltage ASIC technology qualification for space application.

Increasing needs for low costs, low space occupancy and reduced weight in the space industry have made ASIC integration of recurrent functions mandatory. Today, ASICs are used only for digital applications, but for the next satellite platform generation, ASIC integration will also be needed for analogue, mixed-signal and high-voltage applications. Airbus DS selected the XFAB XH035 mixed-signal technology for its modularity and high-voltage extensions. This technology targets automotive, telecommunication and power management markets; therefore it has been widely used and tested for various applications and considered to be a mature technology. Furthermore, digital and mixed-signal ASICs for space applications have already been designed in this technology and their radiation tolerance has been tested but, to our knowledge, the high-voltage functionalities have never been used in this context. Lastly, the cost of a foundry run is compatible with our cost reduction needs, thanks to the selected technology node. The current activity builds on the previous ID-MOS/CNES development dealing with the hardening of the standard Low Voltage XH035 process, by including the high voltage capability. The XH035 High Voltage technology requires a deep epitaxial layer that has an impact on the cell design and thus influences the radiation tolerance of the digital library. All the HV transistors have to be hardened and tested against radiation. To fulfill Airbus DS needs, especially in terms of radiation tolerance, a High Voltage radiation-hardened library has been developed with the XH035 HV technology and is currently under evaluation. For a full characterization and qualification process, a test vehicle has been designed; this test vehicle contains: digital cells, analogue functions and high-voltage transistors (NMOS and PMOS ranging from 15V to 90V). Radiation-hardening consists of implementing ELTs (Enclosed Layout Transistors) surrounded by Guard Rings and with additional spacing between PMOS and NMOS banks. Up to now, SEL (Single Event Latchup), SEB (Single Event Breakdown) and SEGR (Single Event Gate Rupture) tests have been performed and TID (Total Ionizing Dose) and Life tests are underway. After this radiation qualification phase, a precise electrical characterization of the designed cells will be performed to improve the device models. This research and development project is performed for the Neosat project with Airbus DS as prime contractor and is under CNES contract and with ID-MOS for ASIC design.

Speaker: Marc Souyri (Airbus DS)

Paper AMICSA2014_34_Souyri_paper.pdf

Slides AMICSA2014_34_Souyri_slides.pdf

14:40 → 15:20 Poster Session

Convener: Richard Jansen (ESA)

14:40 AFTU, an Analog single event effects automatic analysis tool

AFTU is an End-User Development (EDU) software tool for the analysis of Single Event Effects on microelectronic designs. AFTU takes user inputs as the design netlist, VLSI technology type, injection points and analysis heuristics classes to generate an expert software with two main functions: management of a simulation set through Spectre and a heuristic-based inference engine to classify and analyze the simulation set results. The actual AFTU 1.0 simulates single event effects through current injection models. We present the AFTU tool chain, comprising a user interface, a full compiler from user input to code generator in SKILL language and an end analysis presentation file. The output code is the expert software, to be interpreted by Cadence OCEAN. The process simulation flow, commanded by the expert software, generates a set of simulations of the microelectronic design under several SEE situations, coded as injection models, in different design elements. The simulation set results are organized by the inference engine and selected under heuristic based inferences, in order to present a SEE vulnerability assessment file to the microelectronics designer. For illustration of AFTU capabilities, we present two case studies. First one is a Single Event Transient analysis on a Op-Amp in voltage follower configuration. Second one is a Single Event Upset analysis of a basic Finite State Machine. Both designs are implemented in ST Microelectronics 130 nm technology. In each case there is a specific heuristic, showing the tool versatility. Future improvements are also discussed.

Speaker: Dr Fco. Rogelio Palomo Pinto (Electronic Engineering Dept., Higher Technical School of Engineering, Sevilla University, Spain)

Paper AMICSA2014_AFTU.pdf

Poster AMICSA2014_38_Pinto_poster.pdf

14:40 An ASIC for Spaceborne Radiation Monitors

The IDE 3465 is an application specific integrated circuit (ASIC) that has been designed for the readout of silicon detectors for charged particles. The chip has 20 inputs of charge sensitive pre-amplifiers (CSA), a total of 37 digital logic trigger outputs, and one analogue multiplexer output for pulse heights. Out of the 20 channels, 16 have a high gain with saturation at 2.6 pC, and 4 have a low gain with saturation at 26 pC. In the high-gain channels, the charge sensitive pre-amplifier is connected to one slow shaper of 1-μs shaping time and two fast shapers of 250-ns shaping time, while the low-gain channels have only one slow shaper and one fast shaper of 1-μs and 250-ns shaping time. Each fast shaper output is connected to a comparator, which triggers when the pulse shape exceeds the reference level that can be programmed by 8-bit DACs. The two fast shapers and comparators of the high-gain channels are used for charges in the range from 1 fC to 100 fC and from 100 fC to 2.6 pC, respectively. The fast shapers and comparators of the low-gain channels are designed for charges in the range from 1 pC to 26 pC. Each comparator feeds a mono-stable output, which can be connected directly to an FPGA. The chip requires negative and positive voltage supplies (-2 V, +1.5 V and +3.3 V) and one reference bias current to generate its internal biases. The total power consumption is less than 65 mW, depending on the input event rate and options enabled. The chip has a 356 bit register, programmable via serial interface, which allows one to set various functions, to program digital-to-analogue converters (DACs), and to tune parameters. All amplifier inputs are protected by diodes against over-voltage and electro-static discharge (ESD). The chip is SEU/SEL radiation hardened by design and manufacture. Tests with heavy ion beams show a SEL threshold higher than 116 MeVcm2/mg. The programmable configuration register has been designed to correct for single-event upset (SEU), i.e., each register cell has triple redundancy with a self-correcting circuit and a SEU output signal. The 0.35 µm CMOS process meets the 100-krad total-ionizing dose requirements (TID).

Speaker: Mr Alf Olsen (IDEAS)

Paper AMICSA2014_41_Olsen_paper.pdf

14:40 Analog Front End Integrated Circuits for Mixed Signal Spacecraft Applications

Mixed signal spacecraft systems typically involve a digital processing portion to execute algorithms based on external events and the Analog Front End (AFE) that provides the interface between the benign digital processor environment and the “real world”. The digital processor is typically optimized for high speed computations using a low voltage process that helps reduce the power consumption. The analog interfaces in some applications are higher voltages to minimize susceptibility to interference. The digital processing can be a sequential instruction microprocessor which realizes algorithms in software or an FPGA fabric that can simultaneously process several data streams. An analog front end (AFE) might consist of operational amplifiers, current sources, data converters, power drivers. Typical applications include telemetry for applications including attitude control, motor control and position sensing, and power control. The sensor interface is rarely compatible directly to the processor I/O so some level of buffering is necessary. Buffering is also required to support redundancy which may involve cold sparing. There are various degrees of specialization that can be supported by an AFE; the most flexible being a design made up of single function parts that are uniquely configured for each application. The highest level of integration is a custom IC designed for a specific application; this solution affords the least degree of flexibility if the requirements change. An AFE approach that offers a high degree of integration and a high degree of flexibility would be an integrated circuit with commonly used analog interfaces that are configurable. An efficient partitioning of the analog and digital functions minimizes the hard coded logic within the AFE and moves as much of the configurability to a Hardware Description Language (HDL) defined digital part such as an FPGA. HDL based logic tends to be more intuitive than schematic based logic using LSI parts for example. A spacecraft FPGA is designed to be radiation tolerant with redundant logic paths; it uses a small geometry process to improve circuit density. The FPGA gate count can be sized to an application or a group of applications to reduce cost and increase gate utilization. When the AFE is offered as a standard prequalified part as opposed to a custom part, it has the advantage that it does not require development so non-recurring engineering is reduced and time to market and schedule risk are also reduced. While the standard part AFE may not be fully utilized in every application, the level of integration for using even a portion of the circuits is usually a reduction in size over the use of single function parts. There are many spacecraft functions that can benefit from an AFE. Sensor arrays such as health monitoring are suitable for sequential sampling as opposed to continuous monitoring. A flexible sensor interface AFE includes an analog multiplexer, a conditioning amplifier and an analog to digital converter. Passive sensors require an exciter such as a current source and should support a “four wire” measurement for high accuracy. Maximum flexibility can be designed in by allowing each AFE I/O to serve as a current source, a differential input or a single ended input. A position sensor such as a resolver or a coil current sensor in a motor likely requires continuous sampling if the position and or current is used in a servo control system that also drives the motor coils. A sigma delta converter with oversampling works well in these applications since the sampling modulator can be implemented in the AFE and the filter can be implemented in the FPGA. The FPGA can control the degree of the decimation to obtain a flexible compromise between resolution and sample rate. The FPGA can also process multiple ADC paths simultaneously and not burden the control loop state machine with the ADC sinc3 filter processing. For power control, the non-volatile programming of an FPGA can be exploited to bring up power rails in sequence and to mitigate faults if the occur. The AFE can provide voltage and current supervision and DACs for power supply margining. The AFE can also provide linear control for slewing the output of solid state circuit breakers to reduce power bus transients and open circuits in the event of a fault. The use of a standard integrated circuit AFE paired with a configurable FPGA takes advantage of a high level of integration when the partitioning of the analog and digital functions provides IC process optimization for the implementation of the digital and the analog functions. Higher integration reduces parts count which improves reliability and reduces size and weight of the spacecraft electronic modules. This presentation discusses the topics above and provides examples to demonstrate the concepts.

Speaker: Mr Bruce Ferguson (Electrical Engineer at Microsemi Corp)

14:40 CMOS Analog Front End Design for Particle Energy Measurement in Space Environment

In situ studies of the geospace environment, including space weather monitoring, is mainly based on the measurements of particles and fields. The particle content of the Earth’s magnetosphere is studied with electron and ion detectors in various energy ranges, from the cold and dense eV solar wind to the MeV radiation belts. Here, the in situ high-energy (50 keV to 725keV) electron measurement is targeted. The design and development of space embedded electronic equipment require a specific approach. An Analog-Front-End (AFE) design methodology is proposed to optimize noise, bandwidth, consumption, crosstalk and radiation hardness performances of such AFEs for Si semiconductor detectors. Firstly, it is necessary to perfectly understand the detector and propose an equivalent electrical model. With this aim, the GEANT4 simulator is used to model the various physical effects associated with particles interacting within the Si detector. The number of generated electron-hole pairs can thus be estimated as a function of the incident particle energy. Further, the main electrical characteristics of the sensor such as its charge collection time, its parasitic capacitance as well as its leakage current, can also be retrieved to correctly build an equivalent electrical model of the detector. Then, the choice of the technology should take into account both the space mission duration and the radiation environment characteristics. In addition, the state of the art of radiation hardness by design (RHBD) methods shows in particular that for thin oxide thickness CMOS technology , Total Ionizing Dose (TID) effects are greatly reduced by tunneling mechanism. However, for such technologies, the sensitivity to Single Event Effects (SEE) is increased and the circuit dynamic range is reduced. For missions in low earth orbit, electronic systems must withstand a TID of 20 krad for a period of two years. The 0.35 µm CMOS technology can be chosen because it can naturally withstand more than 50 krad. Also, this technology works with a supply voltage of 3.3 V which allows a high enough dynamic range. Further, to protect circuits from latchups while using standard CMOS technologies, the extensive use of guard rings is required. In addition, to minimize crosstalk and improve power supply rejection, it is useful to use an isolated-well technology. This feature is usually provided by High Voltage (HV) technologies. Finally, a 0,35µm CMOS HV technology has been chosen. Secondly, the designed AFE should quantify the amount of detected charges in order to reconstruct the electron energy spectrum. Consequently, the AFE should have a linear output response to ease the mapping charge-electron energy. The first step is to convert charge into a voltage using a charge preamplifier (CPA). The CPA consists of a transconductance amplifier (OTA) with a feedback capacitance Cf to perform the charge integration. Then, in order to improve the Signal-to-Noise Ratio (SNR), the CPA output voltage is filtered by a circuit called pulse shaper (PS). Therefore, the analog-to-digital converter (ADC) input signal noise is reduced, which thus decreases the detection threshold level and increases the AFE achievable precision.To save power as well as reduce the influence of any external parasitic signals, analog to digital conversions of the CPA+PS output should be performed within the same chip. Thus, each channel has the following architecture: a CPA+PS, a comparator with an adjustable threshold voltage level, a peak detector (PD) and an 8 bits Successive Approximations Register (SAR) ADC. To summarize, the CPA+PS converts the incident charge into a proportional voltage and the comparator detects if the incoming charge is higher or lower than the desired threshold level. Note that the minimum detection threshold level can be obtained by setting the threshold voltage of the comparator just above the noise floor. The PD is used to store the maximal peak value of the PS output voltage, which is proportional to the electron energy. This stored voltage is then digitized by the SAR ADC. A control logic block of the system is also designed to manage the communications between the blocks. The ASIC tests have shown a charge-to-voltage conversion gain of 60 mV/fC for a charge range of 0.6 fC to 32 fC. The equivalent noise charge (ENC) is 3119 e- with an input parasistic capacitance of 40 pF while consuming 2.5 mW. The circuit can perform measurements up to a 650 kHz rate.The next step is to characterize the ASIC associated with the SC detector in a vacuum chamber. Furthermore, the TID and the SEE tolerances must also be evaluated.

Speakers: Prof. Hélène Tap (Université de Toulouse INP LAAS), Dr Olivier Bernal (Université de Toulouse INP LAAS)

Paper AMICSA2014_36_Tap_paper.pdf

14:40 Complementary Presentations from Industry and Institutes: Atmel, Arquimea, INFN, e2v, Sitael, Aeroflex, MIND

Speakers: Bernard BANCELIN (Atmel), Daniel González (Arquimea), Franco Bigongiari (SITAEL S.p.A.), Herve Mugnier (MIND), Mr Nicolas Chantier (e2v), Paolo Carniti (Universita & INFN, Milano-Bicocca (IT)), Mr Sandi Alexander Habinc (Aeroflex)

14:40 Development of an High Speed and High Resolution ADC for Image Processing Applications

Today there is no space suitable solution in Europe for high speed (e.g. 20Msps) and high resolution ‎‎(16 bit) Analogue-to-Digital Converters (ADC) to process and digitise analogue output signals from ‎image sensors or other high resolution instruments. Such devices would enable new applications ‎with higher performance. In addition it would guarantee European independence and it would ‎reduce the dependence on COTS devices and their associated screening costs and time.‎ Therefore ESA has initiated a program for developing such an high-speed and high resolution ADC. ‎In the framework of this program SPACE ASICS (Greek) will develop such an ADC together with ‎Kayser-Threde GmbH (Germany) and others. ‎ The paper will present the project objectives, planning and will define and present the key ‎performance requirements for the ADC under development. Because the ADC application is ‎targeted to image processing with CMOS and CCD sensors an analogue front end is also ‎implemented in the ADC providing typical analogue processing as used for readout of imaging ‎sensors. The paper will present and discuss this analogue front end, including clamping, ‎correlated double sampling and adjustable offset and gain correction. Furthermore all other ‎functional requirements are presented and discussed.‎ Verifying the characteristics of an ADC with such high dynamic performance can prove very ‎challenging as the evaluation environment has to be designed such that it provides even better ‎performance than the device-under-test (DUT). Eliminating any kind of noise caused by signal ‎generators or external circuitry is a key aspect designing the test environment. Additionally, the ‎choice of suitable measurement techniques and test conditions is important for an accurate ‎determination of the performance characteristics and demanded test equipment. The abstract will ‎present verification methods and algorithms and will show previous test results, performed for ‎evaluation of the test environment. Conclusions for testing of the ADC are drawn from the results ‎and evaluation of the acquired data. For each sub-part of the evaluation board including the ‎corresponding signal generators that generates the input signal, solutions are presented how the ‎necessary performance and functionality can be achieved. Furthermore, selected measurement ‎techniques will be presented that have proven to be suitable to verify and characterize the 16-bit ‎analog-to-digital converter and provide a good basis for the development of the final evaluation ‎environment once the prototypes of the ADC are realized.‎ Furthermore the paper shall address potential users of the ADC and shall present the procedure ‎of a market survey to be performed in the framework of the project. Potential users shall be ‎identified and appropriate feedback about performance and functionality of the ADC shall be ‎requested.‎

Speaker: Mr Heinz-Volker Heyer (Kayser-Threde GmbH)

Paper AMICSA2014_13_heyer_paper.pdf

14:40 Scalable Sensor Data Processor: A New Mixed-Signal Processor ASIC for Harsh Environments

In recent years, ESA has pursued the development of technologies for next-generation space Digital Signal Processing (DSP). One of those developments, the Massively Parallel Processor Breadboard (MPPB), demonstrated European DSP cores as well as scalable Network-On-Chip (NoC) technology for large Systems on Chip (SoC) and included space typical features such as SpaceWire interfaces, ADC/DAC bridges and more. In a subsequent activity aimed at development of library elements for IMEC's DARE180 technology, a DSP prototype chip was developed in order to prove the key elements of MPPB in DARE180 based silicon, and pave the way towards future space DSPs based on the demonstrated technologies. The Scalable Sensor Data Processor (SSDP) is the first of a new generation of such processors, featuring an architecture very similar to MPPB (LEON General Purpose Processor (GPP), 2 VLIW Xentium(R) DSP cores, high-bandwidth NoC, space typical interfaces (SpaceWire, ADC/DAC, CAN, SPI and others) for the digital part. Like the prototype, the ASIC will be based on DARE180 technology which allows incorporation of analogue / mixed signal elements. It is expected that several mixed signal blocks will be integrated, such as a fast (100 MHz) ADC for instrument data acquisition, a second slow (ca 100 kHz) ADC with multiplexers for housekeeping data acquisition, and additional circuitry for connection to external sensors. The ASIC will run at a target clock speed of up to 100 MHz, providing in excess of 1 Giga-Ops for 16-bit data and 500 MOps for 32 bit fixed point data. The GPP will provide a floating point unit, and on-chip memories will be provided for fast data access in addition to external memories such as SDRAM, SRAM, and PROM. The ASIC will feature high radiation hardness and reliability as well as low power consumption. The development, which started in Q1/Q2 2014, is expected to provide prototype chips towards the end of 2015, followed by flight models about 1 year later.

Speaker: Roland Trautner (E)

Paper AMICSA2014_07_Trautner_paper.pdf

Poster AMICSA2014_07_Trautner_poster.pdf

15:20 → 15:40 Coffee Break

15:40 → 17:00 Radiation Hardened Technology for Mixed-Signal IC: (3/3)

Convener: Richard Jansen (ESA)

15:40 ATMEL mixed signal space offer: SOI 150nm radiation hardened process

ATMEL is moving towards “fablite” or “fabless foundry”. ATMEL develops its own low power process for Automotive and Space applications in order to control the lifetime and the second sourcing. ATMEL is qualifying its 150nm SOI process. This process offers a radiation hardened digital library, analog cells, NVM, 5V IOs and high voltage transistors. First available will be the 45V high voltage transistor, with a process that is capable of up to 120V. The 150nm CMOS process offers capability of deep N-well and Deep Trench. CMOS process * Core 1.8V and 3.3V devices re-used from ATC18RHA with proven hardening solution * Back-end process flow with Metal1 pitch at 0.40um, providing higher interconnect densities than that of the competition * 5V CMOS (optional) * High Speed and low leakage option Library * Digital radiation hardened library * DAC/ADC * Regulator * Voltage reference * PLL, DLL * Bandgap * RC and XTAL oscillator Memory * SRAM/DPRAM generator qualified in the same MIL range as ATC18RHA * Non Volatile Memory (1 poly EEPROM cell) coming from Automotive technologies 58.9/58.95K * Poly fuses for memory configuration or trimming Power Devices and ESD * Full range of 3.3V LDMOS with low Rdson * High level SEL performance due to the Deep trench isolation and SOI substrate * HV ESD proven structures from Automotive * Thick power metalization (8mOhm/sq) Devices for mixed-signal applications * MIM capacitor * Bipolar NPN/PNP transistors * Zener Diodes * Inductors * High Capacitors * High Poly resistors Qualification results of main elements will be presented. The different design flows will be presented that can be used depending on the share of analog and digital on the die.

Speaker: Mrs Valerie Briot (ATMEL)

Poster AMICSA2014_42_Bancelin_poster.pdf

Slides ATMX150RHA_amicsa2014_-_atmel.pdf

16:00 180nm CMOS Mixed-Signal Radiation Hard Library as base for a full ASIC supply chain

In recent years the importance of mixed-signal ASIC supply for Space Applications in Europe has grown. Since there is a trend that Europe should be more independent from other worldwide sources in obtaining these components on the market. IMST is actually working together with TESAT Spacecom towards a mixed-signal library as part of an ESCC qualified ASIC supply chain. This paper presents the IP blocks of IMST which are developed using innovative design and radiation hardened techniques. These blocks are going to go through a program of evaluation and qualification tests. The radiation hardened library of IMST, called HARD Library (HARD= Hard Against Radiation Design is built from I/O cells for 3.3V and 5.0V supply voltages, reconfigurable multifunctional operational amplifier, voltage and current references, memory cells, data converters and other analog and digital IP blocks, which will be described in this paper. The HARD Library is based on the 180nm CMOS technology from XFAB, which is a modular mixed signal high voltage technology. It supports operation by negative supplies, which is one of the characteristics of the HARD Library elements. Another feature of this technology is offering different modules for low power, high temperature, high voltage and non volatile memory all in one platform. XFAB's 180nm CMOS technology is already tested with good results against radiation effects. In this paper first radiation test results of the IP blocks will be presented as well as scenarios about the design flow of the HARD Library. Since the project is still in progress, evaluation test results are not available yet. Finally the paper will show IMST´s capability to operate as a supplier for full space qualified ASIC`s to the market, handling the full supply chain in one hand.

Speaker: Jan Steinkamp (IMST)

Paper AMICSA2014_10_Steinkamp_paper.pdf

Slides AMICSA2014_10_Steinkamp_slides.pdf

16:20 DARE180X: A 0.18µm mixed-signal radiation-hardened library for low-power applications

DARE180X is a mixed-signal library solution for radiation applications implemented in the low-power 0.18µm commercial technology from XFAB. This set of libraries comprising core standard cells, digital and analog I/O cells, analog IP and SRAM memory blocks is currently being developed using a guard-ring shielding approach to guarantee TID tolerance higher than 100krad as well as SEL hardening up to 60MeV/cm2.mg. The DARE180X core library aims to offer good SEE hardening and low-power consumption capabilities by combining high density standard cells with SET hardened-by-drive-strength combinational cells and SEU hardened-by-design sequential cells. The DARE180X libraries also include a broad list of digital and analog I/O cells as well as several radiation-hardened analog IP blocks such as bandgap, ADC, DAC, PLL, etc. This paper details the development of the DARE180X library and analyses its features and simulation measurements. A comprehensive comparison with the existing DARE180 library solution implemented in the UMC 0.18µm technology is also presented.

Speaker: Mr Giancarlo Franciscatto (imec)

Paper AMICSA2014_27_Francisciatto_paper.pdf

Slides AMICSA2014_27_Francisciatto_slides.pdf

16:40 The development of a radiation tolerant low power SRAM compiler in 65nm technology.

With the upcoming upgrades of the LHC experiments, it will be necessary to improve the performance and reduce the power consumption of the detector readout electronics. CERN has chosen to use a 65nm technology for part the new generation ASICs targeted to these upgrades. For this technology the SRAM memories within the readout circuitries need special attention as the commercially available IP blocks don’t give the necessary radiation tolerance. This paper will describe the design of a technology independent SRAM compiler design platform with a custom SRAM design underneath. The generated SRAMs have clock synchronous write/read operations and pseudo dual-port addressing. They are implemented in the LP (Low Power) version of the technology and are designed to be radiation tolerant to reduce excessive power leakage due to TID (Total Ionizing Dose) and to minimize the impact of SEE (Single Event Effects) in the memory address decoding circuitry. An additional challenge for these SRAMs is to keep the power consumption to a minimum whilst maintaining the radiation tolerance.

Speaker: Mr Robin Brouns (imec)

Paper AMICSA2014_12_Brouns_paper.pdf

Slides AMICSA2014_12_Brouns_slides.pdf

17:00 → 19:00 Free Time

17:00 → 19:00 Social Programme: Atlas Visitor Centor

17:00 Atlas Visitor Center: Group A

Guided Tour through Atlas Control Data Center

18:00 Atlas Visitor Center: Group B

19:30 → 22:30 Social Programme: Workshop Dinner

Tuesday, 1 July

09:00 → 09:30 Keynote

09:00 Using Hybrid Pixel Radiation Imaging Detectors for Space Radiation Environmental and Dosimetric Applications

While it may seem like a retro-application to use hybrid pixel detectors for applications that consist primarily of observing incident charged particles, given the provenance of these detectors in high energy physics, in actuality the challenges faced are surprisingly novel, at least for these devices. While the space radiation environment consists of mainly charged particles, the routinely seen charges of dosimetric interest range from protons through that of fully ionized iron nuclei, and with energies from stopping to very relativistic. In addition, while their fluxes are not necessarily isotropic, as a practical matter, locally they can appear to be incident from any direction with respect to the detectors. Furthermore, the fluences can vary by many orders of magnitude both in location and time. In the end, the ultimate goal is to characterize the charged particle radiation field as completely as possible in order to be prepared to calculate any potential dosimetric endpoint, and to do so with minimum power and external bandwidth requirements. While devices that enjoy access to spacecraft (or even spacesuit) power, detector stacks with multiple layers can be considered, however for portable battery-powered “film-badge” replacements one is pretty much relegated to a single detector device. Using pattern recognition and an thorough analysis of the pixel cluster created in pixel-based device like the Medipix2 Timepix technology, it is possible to measure the track length of an energetic penetrating charged particle as well as the energy deposited, which leads to knowledge of the Lineal Energy Transferred (LET) to the sensor. Further one can determine the polar and azimuthal angles of the track, and by analyzing the δ-rays for more energetic particle’s tracks the propagation direction can inferred. Likewise the δ-rays can give information about the energy (or more correctly the velocity), which when coupled with the LET can give a reasonable estimate of both the charge and kinetic energy of the particle. Some difficulties that need to be overcome include distinguishing crossing tracks, interactions, and stopping particles as well as having to deal with the huge range of potential input charge per pixel including accurate calibration. Results from 5 Timepix units with over a year and a half in orbit on the International Space Station will be presented.

Speaker: Prof. Lawrence Pinsky (University of Houston (US))

Slides AMICSA2014_39_Pinsky_slides.pdf

09:30 → 10:50 Applications for Radiation Hardened Analogue and Mixed-Signal ASICs: Read-Out-IC

Convener: Francis Anghinolfi (CERN)

09:30 FAIR, a front-end ASIC for infrared detector readout

In the FAIR project (Front-end ASIC for Infrared detector Readout), an IC is developed for the readout of state-of-the-art NIR/SWIR detectors for future Earth observation missions and astrophysics. The chip consists of a high-resolution ADC with integrated offset correction and adjustable gain, and voltage regulators to generate bias/reference voltages for the detector. The chip is designed to operate in an extremely large operating range from -218 degrees Celcius up to 50 degrees Celsius. The original mission goal was for the Exoplanet Characterization Observatory (EChO). In order to fulfil the challenging stability and low-noise requirements, the read-out electronics needed to be placed as close to the detector as possible, thus reducing electromagnetic interference (EMI) and gaining overall signal integrity. The close proximity to the cooled detector requires the read-out electronics to operate at an equally reduced temperature. Considering that the target atmospheric gases addressed by EChO - CH4, CO, CO2 and H2O - are the same as addressed by current and future in Earth-observation missions in the SWIR-IR spectral range (e.g. ESA Sentinel-5, ESA CarbonSat, CNES MicroCarb), it is clear that the FAIR chip also offers interesting opportunities for application in future Earth observation missions. The FAIR chip can be placed naturally into the existing electronic readout environment for application to other future IR detectors, replacing and significantly miniaturizing the analog electronics, fitting in the on-going trend of integration in detector electronics for space instrumentation in general: obvious advantages are the reduction of power consumption, volume and weight. The ADC has a 16-bit resolution and offers a sampling rate of 1 Megasample per second. It is designed for an ultra-low power consumption of 16mW. The ADC analog circuitry area is 2 square mm. Special analog layout techniques were used to ensure radiation hardness, and all digital circuitry was place&routed using the rad-hard IMEC DARE library.

Speaker: Dr Jan-Rutger Schrader (SRON Netherlands Institute for Space Research)

Paper AMICSA2014_15_Schrader_paper.pdf

Slides AMICSA2014_15_Schrader_slides.pdf

09:50 Analog Front End Integrated Circuits for Mixed Signal Spacecraft Applications

Mixed signal spacecraft systems typically involve a digital processing portion to execute algorithms based on external events and the Analog Front End (AFE) that provides the interface between the benign digital processor environment and the “real world”. The digital processor is typically optimized for high speed computations using a low voltage process that helps reduce the power consumption. The analog interfaces in some applications are higher voltages to minimize susceptibility to interference. The digital processing can be a sequential instruction microprocessor which realizes algorithms in software or an FPGA fabric that can simultaneously process several data streams. An analog front end (AFE) might consist of operational amplifiers, current sources, data converters, power drivers. Typical applications include telemetry for applications including attitude control, motor control and position sensing, and power control. The sensor interface is rarely compatible directly to the processor I/O so some level of buffering is necessary. Buffering is also required to support redundancy which may involve cold sparing. There are various degrees of specialization that can be supported by an AFE; the most flexible being a design made up of single function parts that are uniquely configured for each application. The highest level of integration is a custom IC designed for a specific application; this solution affords the least degree of flexibility if the requirements change. An AFE approach that offers a high degree of integration and a high degree of flexibility would be an integrated circuit with commonly used analog interfaces that are configurable. An efficient partitioning of the analog and digital functions minimizes the hard coded logic within the AFE and moves as much of the configurability to a Hardware Description Language (HDL) defined digital part such as an FPGA. HDL based logic tends to be more intuitive than schematic based logic using LSI parts for example. A spacecraft FPGA is designed to be radiation tolerant with redundant logic paths; it uses a small geometry process to improve circuit density. The FPGA gate count can be sized to an application or a group of applications to reduce cost and increase gate utilization. When the AFE is offered as a standard prequalified part as opposed to a custom part, it has the advantage that it does not require development so non-recurring engineering is reduced and time to market and schedule risk are also reduced. While the standard part AFE may not be fully utilized in every application, the level of integration for using even a portion of the circuits is usually a reduction in size over the use of single function parts. There are many spacecraft functions that can benefit from an AFE. Sensor arrays such as health monitoring are suitable for sequential sampling as opposed to continuous monitoring. A flexible sensor interface AFE includes an analog multiplexer, a conditioning amplifier and an analog to digital converter. Passive sensors require an exciter such as a current source and should support a “four wire” measurement for high accuracy. Maximum flexibility can be designed in by allowing each AFE I/O to serve as a current source, a differential input or a single ended input. A position sensor such as a resolver or a coil current sensor in a motor likely requires continuous sampling if the position and or current is used in a servo control system that also drives the motor coils. A sigma delta converter with oversampling works well in these applications since the sampling modulator can be implemented in the AFE and the filter can be implemented in the FPGA. The FPGA can control the degree of the decimation to obtain a flexible compromise between resolution and sample rate. The FPGA can also process multiple ADC paths simultaneously and not burden the control loop state machine with the ADC sinc3 filter processing. For power control, the non-volatile programming of an FPGA can be exploited to bring up power rails in sequence and to mitigate faults if the occur. The AFE can provide voltage and current supervision and DACs for power supply margining. The AFE can also provide linear control for slewing the output of solid state circuit breakers to reduce power bus transients and open circuits in the event of a fault. The use of a standard integrated circuit AFE paired with a configurable FPGA takes advantage of a high level of integration when the partitioning of the analog and digital functions provides IC process optimization for the implementation of the digital and the analog functions. Higher integration reduces parts count which improves reliability and reduces size and weight of the spacecraft electronic modules. This presentation discusses the topics above and provides examples to demonstrate the concepts.

Speaker: Bruce Ferguson (Microsemi Corporation)

Paper AMICSA2014_44_Ferguson_paper.pdf

Slides AMICSA2014_44_Ferguson_slides.pdf

10:10 Design and test of MROD, a 2 Channels Video Chain Mixed-Signal ASIC for High Resolution Mission

THALES ALENIA SPACE is the European leader for Satellite Systems and since 1993 the company has been designing and developing an important series of space used Mixed-Analog ASICs. Major actor for high resolution electronics for Earth Observation and Scientific missions, THALES ALENIA SPACE has been granted a CNES contract for the development of a high performance, low voltage CMOS integrated circuit to perform the video chain for CCD and CMOS signals. This circuit is therefore part of the pre-development of the OTOS project (post-pleiades).. This circuit, named MROD, has been released on the XFAB BiCMOS 0,35 μm technology and specific tasks of design hardening have been performed in order to stand for the space radiation environment. MROD design is based on high performances analog block functions (i.e. 12 Mhz/12-14bits) for signal conditioning and digital block functions for DDR signal interfacing and configuration signal interface. It includes 2 fully independent video channels. The present findings will address the following topics: - Missions for MROD (CNES source) - Main specification of MROD - Selection of the CMOS technology - Methodology, design tools - Architecture and Design of mixed signal ASIC MROD - Electrical and radiation test results versus specifications and simulation

Speaker: Mr Philippe AYZAC (THALES ALENIA SPACE, France)

Slides AMICSA2014_28_Ayzac_slides.pdf

10:30 A complete space based CCD biasing solution in a 0.35µm high voltage CMOS ASIC

An ASIC designed to fulfil the role of a general purpose bias voltage generator for CCDs in space based camera systems is presented. The STAR (Space Telemetry And Reference) chip has been developed to reduce both the size and power consumption of the circuitry required to bias a science grade CCD. Implemented in a 0.35µm 50V tolerant CMOS process, STAR provides 24 independent voltage outputs with a 32V range and a SNR of up to 120dB. Each output channel features a 10-bit DAC and a high voltage output buffer to provide current drive of up to 20mA. The output buffer can drive loads of 1KΩ / 10µF, and also includes output current limiting for short circuit protection. An on-board telemetry system featuring a 12-bit ADC and programmable gain buffer allows measurement of the output voltages from the chip as well as up to 32 single ended and 4 differential external voltages. Control of the ASIC is via an SPI interface and all required voltages and currents are generated from internal bandgap circuits. Layout of the circuits uses established radiation hardening techniques with the intent that the circuit be SEL (Single Event Latchup) immune by design. Designed for encapsulation in a 144 pin package the STAR ASIC replaces an entire PCB of discrete electronics in current camera electronic systems. Details of the chip architecture and circuit design will be presented, along with simulated performance and test results.

Speaker: Quentin Morrissey (STFC Rutherford Appleton Laboratory)

Paper AMICSA2014_23_Morrissey_paper.pdf

Slides AMICSA2014_23_Morrissey_slides.pdf

10:50 → 11:10 Coffee Break

11:10 → 12:30 Applications for Radiation Hardened Analogue and Mixed-Signal ASICs: Wired and Wireless Communication

Convener: Francis Anghinolfi (CERN)

11:10 Digital Step Attenuators for Microwave Applications

Digital Step Attenuators (DSA’s) are broadly used within Satellite Payloads to adjust signal levels either as standalone blocks or as a key part of complex systems. Wherever a DSA is employed its critical function is delivering accurate, consistent, repeatable level control in a difficult space environment. The environment in space creates additional challenges due to the wide range of temperatures experienced and radiation. Commercial 7 bit/31.75dB DSA’s have been reported with attenuation errors in the range of (+/-0.1dB + 3% of setting) to (+/-0.15dB + 1.5% of setting) for 8GHz devices. When we investigate these numbers further we find the best attenuation accuracy is typically only achieved over the lower frequency range, typically up to 2GHz. Above these frequencies there are fewer vendors and attenuation accuracy degrades significantly. A 0-13 GHz DSA has been reported with attenuation error of (+/-0.5dB +5% of setting). The attenuation error is highest for the higher attenuation values, to get around this some vendors reduce the maximum attenuation of their DSA’s from 31-32dB to approximately 16dB. The author will review the building blocks of a DSA and describe circuit and packaging solutions to improve attenuation accuracy as frequency increases. Measured results for a 6GHz DSA and an 11 GHz DSA will be compared along with the differences in circuit topology and packaging approach. These results will demonstrate how to achieve improved high frequency attenuation error for Microwave DSA’s.

Speaker: Mr Andrew Christie (Peregrine Semiconductor UK Ltd)

Paper AMICSA2014_22_Christie_paper.pdf

Slides AMICSA2014_22_Christie_slides.pdf

11:30 Low-Power Analogue Receiver ASIC for Space Telecommand Applications

Nowadays, on-board telecommand receivers for space applications consume an important percentage of the overall offered power of the satellite, especially due to their always ON need of operation. Decoders, in charge of elaborating received data and of providing error correction according to redundancy introduced by related encoding protocol are one of the fundamental components of a satellite receiver. They currently follow a digital development approach based on a large FPGA. Even though, initially, the power consumption of digital decoders was not a factor of concern, the increasing communication and data storage complexity and capacity rendered the applicability of error correction codes in a digital domain more and more expensive in terms of hardware resources and power consumption. Therefore, in the last ten years, being analogue decoding recognized for its potential to efficiently decrease the overall power consumption of a receiver, an important growth in analogue decoding research programs is registered, although only a few VLSI integrated circuits have been developed satisfying a given communication standard. Analogue domain implementation of error correction codes, despite its lower power consumption potential with respect to its digital counterpart, seems to also provide some additional advantages: it takes benefit from the similarity between the mathematical operations required by the algorithms and the physical laws governing the circuit; it improves the total system efficiency, because the analogue decoder is much smaller than its digital counterpart and consumes about one order of magnitude less power at the same frequency; it offers high modularity design more immune to noise, by means of differential operation; it offers the capability of providing a finer estimation of the logic state of a single information unit with respect to digital implementations (no quantization); it needs a lower signal to noise ratio to properly correct a wrong input sequence of information unit. Thus, the proposed paper will address such benefits of an on-board analogue decoder implementation by presenting, for the sake of completeness, an analogue receiver chain for telecommand applications for Category A missions (Return-to-Earth, lunar and even Lagrangian missions), being implemented on an ASIC chip. More specifically, despite the analogue decoder component, the ASIC receiver will also include other important blocks of the telecommand reception chain normally accomplished inside an FPGA device, such as IF coherent demodulation stage front end, carrier recovery, baseband clock recovery, data conversion from input SP-L signal codify to NRZ signal codify, Start Frame pattern recognition, analogue memory for input codeword storing and Low-Density Parity Check (LDPC) 128 bit analogue decoder. In particular, LDPC Codes have been chosen as the design basis of the analogue decoder, since they showed in preliminary investigations a big potential for increased power gain when short length codes are concerned as of telecommand communication for Category A missions. Moreover, the analogue receiver will be compliant with the communication protocol described in ECSS-E-ST-50-04C “Telecommand protocols synchronization and channel coding”. In this paper, the architecture of the ASIC is presented and overviewed. In particular, descriptive insights are provided in relation to the implementations of coherent demodulation and decoder basics. Some additional implementation details like schematic-level compact solutions which allow unifying different tasks are highlighted as well. A section is dedicated also to depict the design verification flow followed during receiver development and to highlight the main outputs of the simulations carried out during this activity that provide first high level indications on system behavior and performances. Finally, the layout organization is briefly reported, with particular emphasis on decoder layout issues and adopted solutions. SITAEL S.p.A. has produced all relevant to be presented work in the frame of “RLP_AD: Receiver Low-Power Analogue Decoder” activity (ESA TRP), developed in the context of ESA ITT AO/1-6722/11/NL/GLC with the aim of investigating feasibility of analogue decoding for space applications.

Speaker: Mr Franco Bigongiari (SITAEL S.p.A.)

Paper AMICSA2014_25_Bigongiari_paper.pdf

Slides AMICSA2014_25_Bigongiari_slides.pdf

11:50 Use of IHP's 0.25 µm BiCMOS Process in the Development of European LVDS Devices

Transmission of large amount of data is extensively used in communication among spacecraft and satellite onboard systems during a mission. LVDS (Low-Voltage Differential Signaling) Drivers and Receivers are key to provide means of sending/receiving data along twisted pair cable at very high data-rates with low power and excellent EMI performance. Rad-tolerant and Rad-hard ANSI EIA/TIA 644A complaint LVDS Drivers and Receivers products are essential in an extensive range of space applications. Typical applications with such needs are SpaceWire and clock distribution networks. The purpose of this activity is the development of an LVDS Octal repeater in the frame of ESA’s and ECI’s European LVDS Driver Development intended to be used in space applications and built in IHP’s 0.25-um BiCMOS process technology which has a good performance in terms of radiation, for both total dose and single event effects. Previous tests on this technology show no degradation up to 300Krad of total ionization dose (TID) and a single event latch-up (SEL) immunity up to 84MeV cm2 mg-1 at least. The key features of the octal LVDS repeater include cold sparing (essential for redundant systems architecture), up to 250MHz signaling rate per channel allowing for 500Mbps transfer rates over SpiceWire, 3.3V single power supply, fast propagation delay, low channel to channel skew, TRI-state output control, extended common mode on LVDS receivers and the minimum ESD tolerant rating of 8kV for human body model (HBM), 250V for machine model and +/- 500V for field induced charge device model. In order to validate and characterize the technology for the extended ESD tolerance an additional test vehicle chip has been built in the frame of the activity, with a set of ESD test vehicles that include NMOS clamps, PMOS clams, and diodes.

Speaker: Mr Jesús López (Arquimea)

Paper AMICSA2014_17_Lopez_paper.pdf

Slides AMICSA2014_17_Lopez_slides.pdf

12:10 Rad-hard High Speed LVDS Driver and Receiver

A big challenge in data transmission is the constant increase in data-rate. Low Voltage Differential Signaling (LVDS) is a high speed, low power general purpose standard interface. Our paper presents LVDS driver and receiver circuits specifically designed, packaged and qualified for use in aerospace environment. The intended application of these devices (RHFLVDS31/32 quad drivers/receivers) is point to point baseband data transmission over controlled impedance media with 100 Ω characteristic impedance. A LVDS Driver and a LVDS Receiver have been processed in a 0.13um CMOS STMicroelectronics technology. The Driver accepts low voltage TTL input levels and translates them to low voltage (350mV) differential output signals. The Receiver accepts low voltage (100mV) differential LVDS input signals and translates them to TTL output levels. It can operate over a large common mode input range from -4V to +5V, using a new architecture, to ensure immunity of ground shifting and driver offset voltage, while supply voltage can vary from 3 to 3.6V. To this purpose, the common voltage input is sensed and adjusted to a fixed reference voltage 1.5V with an integrator loop and a class AB transconductor. These devices support data rates of 400 Mbps or equivalently a 200 MHz signal. These two LVDS circuits are designed for space applications. A total ionizing dose test campaign on elementary components has been performed to investigate the technology radiation hardness. The components have been radiated at high dose rate using a C060 gamma ray source. Specific mitigation techniques to achieve best in class hardness to total ionization dose and heavy ions have been applied. Moreover, the chosen technology has a substrate with very low resistivity which is very useful to decrease risks of latch up in general and more specifically Single Event Latch up. One major challenge of these LVDS circuits has been to meet particular ESD specifications which were 16kV on LVDS receiver input and driver output combined with SEL immunity. Laser tests have been useful to best understand their behavior regarding latch up. Both the Receiver and Driver have been evaluated in laboratory. Huge efforts and specific equipment have been necessary to measure properly propagation delays close to 1.7ns with good accuracy (better than 100ps). Finally, 300 krad in high dose rate and 150krad in low dose rate radiation tests have been performed successfully. Heavy ion Single Events Effects tests have also been performed with good results.

Speaker: Mr Thierry MASSON (STMicroelectronics)

Paper AMICSA2014_02_Masson_paper.pdf

Slides AMICSA2014_02_Masson_slides.pdf

12:30 → 14:00 Lunch

12:30 → 14:00 Social Programme: Atlas Underground Visit

12:30 Group 3

13:15 Group 4

14:00 → 15:20 Applications for Radiation Hardened Analogue and Mixed-Signal ASICs: Power

Convener: Richard Jansen (ESA)

14:00 Radiation Tests of Point-of-Load DC-DC Converter and Extended Common Mode LVDS Components

In this paper the results of SEE tests on European Point-of-Load DC-DC converter and Extended Common Mode LVDS components using TFSMART2 technology will be presented. TFSMART2 is an HV BCD technology on SOI with the smallest feature size of 0.35μm. During the AMICSA 2012 conference an unbiased TID radiation test of this technology using the same components has been presented. This paper will follow-up with new results. Currently running low dose-rate biased TID test will also be presented, if finished until the conference.

Speaker: Mr Volodymyr Burkhay (Space IC GmbH)

Slides AMICSA2014_32_Burkhay_slides.pdf

14:20 A radiation-tolerant Point-of-Load buck DCDC converter ASIC

The High Energy Physics Experiments at the Large Hadron Collider (LHC), the most powerful particle accelerator installed at CERN in Geneva, Switzerland, are in an exciting data taking phase but are also preparing upgrades to improve their performance. Their complex assemblies of detector systems make extensive use of electronics components located in a severe radiation environment and in a magnetic field of up to 40,000 Gauss. Power distribution is a real challenge: other than radiation and magnetic field tolerant, the distribution network components have to be small and light (low mass and footprint) and have EMC performance sufficient not to affect the low noise of the sensitive read-out electronics. For this application, CERN has developed a custom Point-of-Load (POL) DCDC converter satisfying all the above requirements. The POL converter is a single-phase buck topology built around an ASIC designed by CERN in a commercial CMOS technology with high voltage capabilities. This circuit, named FEAST2, embeds on the same 2.8 x 2.88 mm2 silicon both the power switches, bootstrap diode and the control circuitry. Capable of operating from an input voltage of 5 to 12V, it has a selectable output voltage range between 0.6 and 5V and can provide up to 4A of output current (within the limit of 10W output power). The switching frequency can be selected in the range of 1-3MHz, the best compromise between efficiency and EMC performance being reached at around 1.8MHz. The bandwidth of the feedback loop, at 150kHz, is sufficiently large to ensure excellent transient regulation. The high switching frequency makes it compatible with the use of small air-core inductors of 200-400nH, which are required to enable its use in the 40,000 Gauss magnetic field of the LHC experiments. In terms of protection features, the circuit integrates a cycle-by-cycle Over-Current Protection (OCP) and an Over-Temperature Protection (OTP), as well as Under-Voltage Lock-Out (UVLO) preventing the converter to turn on in the absence of a sufficient input voltage. Communication with the system embedding the DCDC is ensured by an Enable input (to turn it on/off) and a PowerGood (PG) output flag, both signals being compatible with CMOS logic levels up to 3.3V. The PG is asserted when the output voltage is in the range of +-6.5% around the nominal. Radiation tolerance is achieved with a careful choice of the used CMOS technology (5 candidate processes were probed for different radiation effects) and with the systematic use of hardness-by-design techniques. Enclosed Layout Transistors (ELTs) have been employed to limit Total Ionising Dose (TID) effects in all the control electronics, while adequate sizing, triplication and other appropriate redundancy mitigate the impact of Single Event Effects (SEE). As a result, the circuit has been qualified for TID levels in excess of 200Mrad(SiO2) and for displacement damage up to 5-8e14 n/cm2 (1MeV-equivalent neutrons). SEE qualification has been performed at the high penetration heavy ion beam of CRC, Louvain-la-Neuve, up to an effective LET of 65 MeVcm2mg-1. No destructive events have been ever observed on any of the successive generations of prototypes exposed, evidencing how the devices available in the technology are free from Single Event Burnout (SEB) or Gate Rupture (SEGR). Actually the high voltage transistors have been also directly tested for SEB sensitivity at the beginning of the development. The last and production-ready revision of the circuit, FEAST2, is also free from any Functional Interrupt (SEFI): the converter continuously provided on-specs output voltage while exposed to a cumulative fluence of 126e6 ions/cm2 in the LET range between 10.2 and 65 MeVcm2mg-1. During the irradiation, occasional transients were observed at the output of the converter, of an average duration below 2us and of amplitude below +10%/-20% of the nominal output voltage. This result was possible after having deeply studied the sensitivity of previous prototypes, in particular using pulsed laser to map the sensitive nodes. The FEAST2 ASIC is now fully qualified as production-ready, and its production and distribution to the HEP experiments in the form of a full plug-in DCDC module is starting in the second quarter of 2014.

Speaker: Federico Faccio (CERN)

Paper AMICSA2014_11_Faccio_paper.pdf

Slides AMICSA2014_11_Faccio_slides.pdf

14:40 A mix-signal radhard micro-controller: DPC

Thales Alenia Space is engaged in the development of a radiation hardened mixed-mode circuit: the DPC (digital programmable controller). This device is a major breakthrough in the availability of radiation hardened highly integrated micro-controller. The construction of the DPC is the result of 4 party project involving Imec, ICsense & Thales Alenia Space under an ESA development. This component uses the Imec RHBD DARE on UMC 0.18µ library and analog IP designed full custom by ICsense. The effective performance characterization of the DPC is currently evaluated in Thales Alenia Space laboratory. The DPC is an essential building block for the development of intelligent RTU and other (power) distribution units in LEO & GEO satellites. Its large set of communication interface makes it usable in a broad range of applications such as scientific payload control, motors, actuators, battery management, power management … wherever a decentralized control makes the overall solution more efficient. The presentation covers the key features of the DPC that have been made possible thanks to some extensions of the DARE library such as DPRAM, IO and clock gating. The analog functions such as ADC, DAC, PLL & band gap have been designed such as to minimize the amount of external components needed around DPC (target being a system on chip). The E2prom containing the hardware configuration bitstream and the firmware remains, for this 1st generation, still an external device. Extreme care was taken to SET hardening of the critical analog functions: ICsense having developed automated & systematic charge injection verifications. First tests results will be presented together with the roadmap to complete the evaluation for space use and the path to deliver flight models. **Project organisation** Imec not only has provided the RHBD DARE on UMC 0.18µ library, but also extended it with additional features. Dual port memories are being used to transparently perform memory scrubbing in a seamless manner for the processing unit. The DPC embeds 95Kbytes of memory split over several banks. Clock gating cells have been also added. As the DPC embeds a large range of features, power consumption may become an issue if all of them would be active simultaneously. At boot time, a hardware configuration is loaded in the circuit to only deliver clock toward functions relevant to the target application. Imec also performed top level layout integrating digital netlist & analog macros, performing DRC to check for compliance to particular radiation hardening rules and finally the interface with UMC foundry. ICsense has designed a large set of analog IP blocks which are included on chip. Concerning IO offered to the user, there are 4 analog to digital converters 13bits-1MSps with input multiplexing functions. There are also 3 current steering DAC each 12bits-50kSps / 8 bits-1MSps. As supporting function the DPC also includes an on-chip 100kHz RC oscillator for applications that do not require high precision frequency reference. This frequency reference is internally multiplied with a PLL delivering the internal master clock of the circuit. All these function are obviously supported by an on-chip bandgap. A set of internal low-drop voltage regulators converts the incoming 3.3V into +1.8Vdc to supply the digital core and to deliver “noise-less” supply to critical analog functions. This extensive set of analog function makes DPC a rather standalone system-on-chip (exception being for now the external E2prom). Besides classical RHBD rules such a guard rings (Latchup) & margins for Vt shifts (dose up to 100krad), ICsense has developed an powerful set of extension on top of (Cadence/Mentor) simulation tools to perform systematic charge injection verifications on each nodes of the circuit. ICsense has completed the design, layout & verifications. The 2 analog macros were delivered to Imec for integration into the final chip layout. Thales Alenia Space Belgium has developed the RTL code to glue up all IP: the 16bits OpenMSP430 processor, mil-1553b, UART, CAN interfaces, memories, multipliers... On top of the classical simulation at RTL, the DPC has been extensively validated on 2 FPGA platforms. The first one was used to validate all interaction modes foreseen in the DPC feature list. The second one was to integrate the DPC with its software development environment. Challenge for such a complex mix-mode design resides into the verification of interfaces between analog macros and digital functions. This problem was tackled by the exchange of Wreal models simulating the behavior of analog functions to be used in digital simulations. In the other way, stubs of RTL code have been delivered to simulate analog functions with their interface to digital functions. Foundry was done by UMC & packaging has taken place at HCM. Wafer probe & package testing used facilities of µTest. The component is now back into the labs & alive: tests ongoing.

Speaker: Mr Marc Fossion (ThalesAleniaSpace)

Paper AMICSA2014_19_Fossion_paper.pdf

Slides AMICSA2014_19_Fossion_slides.pdf

15:00 How chips paved the way to the Higgs particle

Speaker: Erik Heijne (Czech Technical University (CZ))

Slides AMICSA2014_45_Heijne_slides.pdf

15:20 → 15:40 Coffee

15:40 → 16:20 Data Converters

Convener: Agustin Fernandez Leon (ESA)

15:40 RCADA - 65nm 12b 3Gspc Rad Hard dual ADC dual DAC

The RCADA mixed signal chip is currently under development by Ramon Chips and Silantrix, combining the rad-hard RadSafe™ libraries and methodologies from Ramon Chips and Silantrix proprietary architecture for data converters. The extreme wideband capabilities of RCADA require very high performance digital processing (for pre-processing and for “digitally assisted analog” methods), as well as high bandwidth digital communication capabilities (to enable low power and low mass transmission of the digital data), to be provided by RC64, Ramon Chips’ many core DSP processor. The two devices will be integrated in an advanced, high-performance multi-chip module (MCM). The key capabilities of RC64 will be presented. RCADA is a multi-purpose data converter that aims to support all high performance applications in advanced space missions including telecommunication, SAR, navigation and earth observation. RCADA integrates two matched ADC cores, 1.5Gsps 12b each, which can be interleaved, forming a single 3.0Gbps 12b ADC. Similarly, it includes two DAC cores, which can be configured as either a dual 1.5Gbps 12b DAC or as a single 3.0Gbps DAC. It can also be configured as a single ADC and a single DAC, 1.5Gbps 12b each, operating simultaneously. Within the MCM, RCADA interfaces RC64 via 48 pairs of bi-directional LVDS buffers, operating at 750Mbps each. RCADA will be fabricated using 65nm CMOS technology. It will operate with 1.2V and 2.5V supplies. Target power consumption is less than 450mW. It will be qualified to MIL-STD-883 Class Y. It will provide very high immunity to TID and to latchup and no sensitivity to single event effects.

Speaker: Mr Tuvia Liran (Ramon Chips)

Paper AMICSA2014_30_Liran_paper.pdf

16:00 Very High Resolution Analog-to-Digital Converter at 1 kHz for Space Applications

We present a monolithic, very high resolution analog-to-digital converter suitable for high precision space applications. The converter is a low-noise, low sampling rate, radiation hardened device optimized to operate in a frequency range from 0.1mHz to 1kHz with nominal output sampling frequency of 6 kHz. The ADC receives a differential voltage input and outputs 24-bit word samples. A simple serial output interface is used. The converter operates on a single clock domain. System architecture is based on a 2nd order, discrete-time (switched capacitor) Sigma-Delta modulator with a 1-bit quantizer and oversampling ratio of 64 to 2048. The first integrator features Correlated Double Sampling to defeat flicker noise and perform auto-zeroing function. The modulator is followed by a decimation filter which reduces the sampling frequency by a factor of the oversampling ratio, to the nominal output sampling frequency. The Decimator consists of a 4th order SINC decimation stage with a programmable factor of up to 128 followed by four cascaded stages of Half-Band filters realizing a factor of 16. Sampling rates up to 96kHz are possible thanks to the selectable oversampling ratio. The theoretical discrete-time model exhibits a Signal-to-Quantization ratio of 141 dB, with the target SNR to be at least 113dB over the entire temperature range. The converter has been implemented in a radiation tolerant 0.15μm CMOS process of Atmel using a well established and rigorous mixed-signal design flow. The analog part has been hardened using dedicated process options, specific devices and special design rules. The digital part has been hardened using hardened standard cell libraries and triple-mode redundancy in all blocks.

Speaker: Mr Konstantinos Makris (ISD S.A.)

Paper AMICSA2014_06_makris_paper.pdf

Slides AMICSA2014_06_makris_slides.pdf

16:20 → 16:50 Wrap-Up

Convener: Agustin Fernandez Leon (ESA)

16:20 Wrap Up

Speakers: Agustin Fernandez Leon (ESA), Boris Glass (European Space Agency)

Slides AMICSA2014_46_Fernandez-Leon_slides.pdf

17:00 → 17:45 Free Time

17:00 → 17:45 Social Programme: Atlas Underground Visit

17:00 Group 5