Speaker
Description
Summary
For run 2 of the LHC, the ATLAS Level-1 trigger system will include
topological information on trigger objects in order to cope with the
increased trigger rates. A dedicated Level-1 Topological Trigger
Processor (L1TOPO) has been developed for that purpose. Although the
Muon-to-Central-Trigger-Processor Interface (MUCTPI) is planned to be
replaced only for run 3 of the LHC in order to provide full-granularity muon candidate information to the L1TOPO, the existing
MUCTPI has already been modified now to provide coarse-grained
topological information on muon candidates. A MUCTPI-to-Level-1-Topological-Processor interface (MuCTPiToTopo) has been developed to receive the electrical information from the MUCTPI system, to collect it, to convert it, and to send it to the L1TOPO on an optical link.
This poster will describe the modifications to the MUCTPI and the
development of the MuCTPiToTopo interface and of the L1TOPO up to the
receiving part. Some details on the firmware development for encoding
of the muon candidate topological information in the MUCTPI, the
serialisation of the information at 320 MHz, the sending over NIM
outputs existing in the current MUCTPI, and the testing of receiving
the information with an FPGA development kit and dedicated firmware
will be described as well as other functional tests. This poster will
further present results of connection tests between the MUCTPI and the MuCTPiToTopo interface, the MuCTPiToTopo interface and the L1TOPO, as well as the full chain and provide typical bit error rates and bathtub plots proving the comfortable margin for the operation of the data transfer.
