Jean-Pierre Cachemiche
(Centre National de la Recherche Scientifique (FR))
22/09/2014, 14:15
Other
Claude Pierre Colledani
(Institut Pluridisciplinaire Hubert Curien (FR))
22/09/2014, 14:30
IN2P3 promotes and unifies research activities in subatomic physics. It coordinates programs on behalf of the CNRS and Universities and has a partnership with CEA. For its experiments and international collaborations, IN2P3 has strong and long standing capabilities in developing, deploying and supporting a wide variety of instruments, from detectors up to the associated electronics. In order...
Vincent Bertin
(Centre National de la Recherche Scientifique (FR))
22/09/2014, 15:15
The ANTARES Collaboration is operating a large undersea detector installed by 2500m depth off the Mediterranean coast of France. Completed in 2008, ANTARES is the largest neutrino telescope of the Northern hemisphere and the first one ever built in the sea. It aims at opening a new observational window over the Universe by looking for high energy cosmic neutrino events. The ANTARES cabled...
Andrew James Whitbeck
(Fermi National Accelerator Lab. (US))
23/09/2014, 09:50
The VME-based data acquisition electronics of the CMS hadron calorimeters will be replaced with a μTCA-based system starting in 2014 and continuing through 2018. The primary new components are the μHTR and AMC13 modules. The μHTR buffers data from the detector and creates trigger primitives. The AMC13 accepts the clock and trigger from the global DAQ system, distributes the clock to the...
Dr
Giulio Usai
(University of Texas at Arlington (US))
23/09/2014, 10:15
The Tile Calorimeter (TileCal) of the ATLAS experiment is the hadronic calorimeter designed for energy reconstruction of hadrons, jets, tau-particles and missing transverse energy. An overview of the on-detector and off-detector TileCal electronics used for ATLAS data taking is given. Upgrade plans for TileCal electronics for the High Luminosity LHC programme in 2024 are discussed, together...
Giovanni Mazza
(INFN sez. di Torino)
23/09/2014, 10:15
ToPiX v4 is the prototype for the readout of the silicon pixel
sensors of the Micro Vertex Detector for the PANDA experiment.
ToPiX provides position, time and energy measurement of the
incoming particles and is designed for the trigger-less
environment foreseen in PANDA. The prototype includes
640 pixels with a size of 100x100 um2, a 160 MHz time
stamp distribution circuit to measure...
Dr
Frederic MOREL
(IPHC-IN2P3, UDS)
23/09/2014, 11:10
Two CMOS Pixel Sensors (CPS) flavours: MISTRAL and ASTRAL, dedicated to the upgrade of the Inner Tracking System (ITS) of the ALICE experiment are being designed at IPHC in Strasbourg. Each of two sensors is composed of three identical units called FSBB (Full Scale Building Block), multiplexed towards the external word. This paper will show the design and the laboratory test results of FSBB-M...
Remi Jean Noel Cornat
(Ecole Polytechnique (FR))
23/09/2014, 11:10
Particle Flow Algorithm (PFA) and highly granular
calorimeters can achieve the best jet energy resolution aiming at precise physics measurements. As shown by years of R&D within the CALICE collaboration the silicon-tungsten imaging electromagnetic calorimeter provides the best
granularity, stability and jet resolution. Our concept has been selected to compete for the upgrade of the CMS...
Isabel Ojalvo
(University of Wisconsin (US))
23/09/2014, 11:35
In 2015 the LHC will resume operations with a center-of-mass energy at 13 TeV and significantly higher Pile Up than previous runs at the LHC. In order to operate under these challenging conditions, CMS is upgrading its calorimeter trigger in two stages: the Stage 1 upgrade will be used in 2015 and integrated with the legacy system. Scheduled for 2016, Stage 2 will have an improved position and...
Philippe Farthouat
(CERN)
23/09/2014, 14:00
To further extend the ultimate physics reach of the experiments at the Large Hadron Collider (LHC), a series of accelerator and experimental upgrades are planned in 2014 (phase 0), 2018 (phase 1) and 2023 (phase 2). The phase 2 machine upgrade, called the High Luminosity-LHC (HL-LHC), is foreseen to increase the instantaneous luminosity by a factor five with a total integrated luminosity of...
Theresa Obermann
(Universitaet Bonn (DE))
23/09/2014, 14:50
New monolithic pixel detector concepts, which integrate the front-end circuitry and the sensor on the same silicon substrate, are being explored for track reconstruction in future particle physics experiments. The innovative concept of Depleted Monolithic Active Pixel Sensors (DMAPS) is based on a high resistive silicon bulk material enabling full substrate depletion with creation of an...
Jason Gilmore
(Texas A & M University (US))
23/09/2014, 14:50
We have built and installed new front-end trigger electronics for the Cathode Strip Chambers in the CMS Endcap Muon system that will efficiently handle the increased data rate in the forthcoming High Luminosity LHC accelerator upgrade. Maintaining trigger efficiency in the forward region requires deployment of higher performance electronics and an improved trigger algorithm. We report on the...
yifan yang
(Universite Libre de Bruxelles)
23/09/2014, 15:15
We will present the readout system being designed for the LCTPC (Large Prototype TPC) for the future ILC. A CPLD resident on a MCM(Multi-chip Module) board will be used to concentrate data from 8 SALTRO chips on the same board and transfer them to a SRU(Scalable Readout Unit) via a serial DTC(data, trigger, control) link, in the final system there will be 75 MCM boards sit on 3 pad module...
Marek Idzik
(AGH University of Science and Technology (PL))
23/09/2014, 15:40
Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout ASIC. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. The ASIC front-end comprises a charge preamplifier and a shaper. Fast shaping is required ($T_{peak}=25ns$, fast recovery) to distinguish between the LHC bunch crossings....
Chengxin Zhao
(University of Oslo (NO))
23/09/2014, 15:40
This paper will present the first results from irradiation tests performed on the ALICE TPC Readout Control Unit 2 (RCU2). The RCU2 is developed in order to double the readout speed with respect to the present RCU1, which then will fulfill the requirements for LHC RUN2.
While the present RCU1 is based on an SRAM based FPGA, which configuration memory has shown to be sensitive to single event...
Peter Phillips
(STFC - Rutherford Appleton Lab. (GB))
23/09/2014, 16:30
The first batch of wafers of ABC130, a Front End ASIC for the ATLAS Silicon Strip Upgrade in IBM 8RF 130nm CMOS technology, were received in November 2013. A design error with the bidirectional SLVS transceiver blocks was identified and corrected, then the design was resubmitted. The corrected wafers are expected to be delivered in June 2014.
The poster will describe the custom driver...
Dr
Christophe Flouzat
(CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
23/09/2014, 16:33
The new 64-channel DREAM (Dead-timeless Readout Electronics ASIC for Micromégas) chip has been designed to read the Micromégas tracker of the CLAS12 experiment. Each channel associates a low noise very frontend part, optimized for large detector capacitances (150pF range), together with a 512-cell analogue memory, ensuring both a trigger latency and derandomization bufferization, allowing a...
Mr
Javier Rodriguez Samaniego
(IFIC)
23/09/2014, 16:34
NEW is the second phase of NEXT, an experiment aiming at searching neutrinoless double-beta decay. Neutrinoless events can only be told from very close energy background events by using to a topological signature produced at the SiPM tracking plane, making this one of the strongest features in NEXT: a high background rejection. The present work describes in detail the front-end electronics in...
Yasuyuki Horii
(Nagoya University (JP))
23/09/2014, 16:35
The Level-1 trigger for muons in ATLAS is based on trigger chambers (RPCs, TGCs) with excellent time resolution which are able to identify muons coming from a particular beam crossing. It is proposed to use precision tracking chambers (MDTs) for improving the transverse momentum resolution at the Level-1 trigger for the phase II of the LHC, the so-called High-Luminosity LHC. We present the new...
yifan yang
(Universite Libre de Bruxelles)
23/09/2014, 16:36
We will present a multi-points wireless temperature monitoring system being designed for the optohybrid for the CMS forward moun detector upgrade project. Optohybrid is a readout board which will be installed inside CMS to control 24 front-end electronics chips and transfer the concentrated data to off-detector electronics through high speed optical fiber. An efficient cooling system is...
Karol Krizka
(University of Chicago (US))
23/09/2014, 16:37
The ATLAS Fast TracKer is a hardware-based track finder for the ATLAS High Level Trigger. Pattern recognition and preliminary track fitting are performed by VME Processing Units consisting of an Associative Memory Board (AMB) containing custom associative memory chips for pattern recognition, and the Auxiliary Card (AUX), a powerful rear transition module which formats the data for the AMB...
Dmitry Osipov
(NRNU MEPHI)
23/09/2014, 16:38
The design considerations on ADCs as a building block for mixed-signal read-out ASICs in high energy physics are presented. The choice of successive approximation architecture is justified as optimal in terms of a power-speed trade-off, arising in multi-channel data acquisition systems for up-to-date physical experiments. As an example, the development of an area-efficient SAR ADC in 180nm...
Christian Amstutz
(KIT - Karlsruhe Institute of Technology (DE))
23/09/2014, 16:39
A simulation framework has been developed to test and characterize algorithms, architectures and hardware implementations of the vastly complex track trigger processor foreseen for the high luminosity upgrade of the CMS experiment at LHC. High-level SystemC models of all system components and input data from physics simulations have been used to evaluate figures of merit, like delays or...
Eduard Atkin
(NRNU MEPHI)
23/09/2014, 16:42
The goal of the NUCLEON satellite mission is the measurements of the elemental energy spectra of high-energy (10**11 -10**15 eV) cosmic rays. It requires a high dynamic range of the readout electronics. The silicon strip detectors were used, the readout ASIC developed and both placed on the ladder. The ADC, data control interface, detector loads, high voltage distributer and service...
Pedro Miguel Vicente Leitao
(FCT Fundacao para a Ciencia e a Tecnologia (PT))
23/09/2014, 16:43
A radiation-tolerant ASIC is being designed for LHC clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR) with determinist phase and low jitter. It operates in two FM modes: either generating 40, 120 and 240MHz outputs (for GBT-FPGA applications) or providing 40, 80, 160 and 320 MHz (for TTC and eLinks applications). The CDR operates with 40, 80, 160 or 320Mbit/s data...
Jose Luis Sirvent Blasco
(University of Barcelona (ES))
23/09/2014, 16:45
A high reliability Buck DC/DC converter, ready to be used on several CERN electronic boards equipped with FPGAs, has been designed and verified. Long lifetime design, according to CERN requirements, has been implemented by minimising component stress with 50% derating. It is a compact power supply module of 16 x 19 mm, which can deliver up to 6A with 95% efficiency.
Its main features include...
Dr
Liang Zhang
(Shandong University)
23/09/2014, 16:46
The first CMOS pixel sensor prototype integrated with 4-bit column-level ADC for the outer layers of the ILC vertex detector has been fabricated and tested. The design is adapted to an original concept of minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. Inside each pixel an amplification stage with a correlated double sampling is used. At the bottom of...
Gilles De Lentdecker
(Universite Libre de Bruxelles (BE))
23/09/2014, 16:47
We will present the readout system being designed for triple-GEM detectors that should be installed in the CMS muon endcap system for the LHC high luminosity phase. The system takes full advantage of current generic developments introduced for the LHC upgrades: micro-TCA, MP7 and AMC13 boards, Versatile Link, GBT, etc. Some hardware components have to be specifically designed: the VFAT3 chip,...
Mehmet Ozgur Sahin
(Deutsches Elektronen-Synchrotron (DE))
23/09/2014, 16:49
The CMS hadron calorimeter detector control system provides 40.08 MHz LHC clock to the front end electronics as well as supplying synchronization signals and I2C communication. Pedestals and diagnostic bits are controlled, and temperatures and voltages are read out. SIPM temperatures are actively stabilized by temperature readback and generation of correction voltages to drive the Peltier...
Jim Hirschauer
(Fermi National Accelerator Lab. (US))
23/09/2014, 16:50
The CMS experiment will upgrade the photodetection and readout systems of its hadron calorimeter through 2018. A central feature of this upgrade is the development of two new versions of the QIE, a custom ASIC for measurement of charge from detectors in high-rate environments. With 3 fC sensitivity, 17-bits of dynamic range, a time-to-digital converter with sub-nanosecond resolution, and...
Sebastian Stefan Feger
(CERN)
23/09/2014, 16:51
This work presents the software environment surrounding the GBT chipset, addressing the requirements of GBTX, GBLD and GBT-SCA. The GBTX is a high speed bidirectional ASIC, implementing radiation hard optical links for high-energy physics experiments. Having more than 300 8-bit configuration registers, it poses challenges addressed by a wide variety of software components. This software keeps...
Konrad BRIGGL
(Heidelberg University)
23/09/2014, 16:53
We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end "KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit resolution is required. For calibration purposes, a 12-bit quantization...
Datao Gong
(Southern Methodist Univeristy)
23/09/2014, 16:55
We present the design and test results of a digital encoder ASIC, LOCic, for high-speed serial data transmission in ATLAS LAr calorimeter readout upgrade. This chip implements a low latency and low overhead line code. The user data is scrambled and encoded into a 128-bit data frame including CRC for error detection. The encoder overhead is 12.5%. A 12-bit BCID information is embedded in the...
David Gascon
(University of Barcelona (ES))
23/09/2014, 16:56
A versatile and reconfigurable ASIC implementing multiple concepts of low level trigger (L0) for Cherenkov telescopes is presented. Two different Level-0 approaches have been included in the L0 ASIC: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analog clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger...
Dr
Arno Gadola
(Physik-Institut, Universität Zürich)
23/09/2014, 16:57
The Cherenkov Telescope Array (CTA) is the next generation ground-based observatory for cosmic gamma rays. The FlashCam camera for its mid-size telescope introduces a new concept, with a modest sampling rate of 250 MS/s, that enables a continuous digitization as well as event buffering and trigger processing using the same front-end FPGAs. The high performance Ethernet-based readout provides a...
Nicola Pozzobon
(Universita e INFN (IT))
23/09/2014, 16:58
The High Luminosity LHC (HL-LHC) is expected to deliver a luminosity in excess of 5x10^34 cm^{-2}/s. The high eventrate places stringent requirements on the trigger. A key component of the CMS upgrade for the HL-LHC is a track trigger to identify tracks with transverse momentum above 2 GeV already at the first-level trigger within 5 us. This presentation will discuss a proposed track finding...
Gianluca Traversi
(Universita e INFN (IT))
23/09/2014, 16:59
This work presents the design of a low-power, differential signaling, input/output data link in a 65 nm CMOS process for high-energy physics (HEP) experiments. The proposed driver is able to operate at 320 Mbps or 640 Mbps achieving a normalized power dissipation of 1.875 mW/Gbps. A pre-emphasis technique has been adopted to reduce the impedance mismatch between the driver output and the...
Alessandro Caratelli
(Sezione di Pisa (IT))
23/09/2014, 17:00
This work describes a radiation tolerant, monitoring and control ASIC for applications in HEP experiments. The GBT-SCA is part of the GBT optical link chip-set. Its purpose is to distribute control and monitoring signals to the on-detector front-end electronics for the upgrades of the LHC experiments. It is designed employing radiation hardening techniques and is fabricated in a commercial...
Mr
Jean-Baptiste Cizel
(LLR/Weeroc)
23/09/2014, 17:01
Building blocks in the Silicon On Insulator 0.18 μm X-fab technology have been designed to study the future generation of SKIROC2 ASIC. These blocks are designed to characterize this technology as a possible candidate for the design of the final read-out ASIC of the Silicon Tungsten (SiW) Electromagnetic Calorimeter (ECAL) foreseen at the International Linear Collider. The performance of these...
Dr
Markus Friedl
(Austrian Academy of Sciences (AT))
23/09/2014, 17:02
At the heart of the Belle II experiment at KEK, there is a Vertex Detector composed of 2 layers of DEPFET pixels (PXD) and 4 layers of double-sided silicon strip detectors (SVD). The latter use APV25 front-end chips, originally developed for CMS, which are run in the so-called *multi-peak mode* that delivers several samples along the shaped waveform. Those are processed in the backend firmware...
Cairo Caplan
(CBPF - Brazilian Center for Physics Research (BR))
23/09/2014, 17:05
The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control...
Mitchell A. Cox
(University of the Witwatersrand)
23/09/2014, 17:06
The Large Hadron Collider at CERN generates enormous amounts of raw data which present a serious computing challenge. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design...
Stefano Magnoni
(Universidad de Oviedo (ES))
23/09/2014, 17:07
CLIC is a world-wide collaboration to study the next “terascale” lepton collider, relying upon a very innovative concept of two-beam-acceleration. This accelerator, currently under study, will be composed of the subsequence of 21000 two-beam-modules. Each module requires more than 300 analogue and digital channels which need to be acquired and controlled in a synchronous way.
CLIC-ACM is the...
Dr
Dirk Wiedner
(Ruprecht-Karls-Universitaet Heidelberg (DE))
23/09/2014, 17:08
Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay mu->eee. In order to reject both combinatorial and physics background, decay vertex position, decay time and particle momenta have to be precisely measured. A pixel tracker based on 50 um thin high voltage monolithic active pixel sensors (HV-MAPS) in a magnetic field will deliver precise vertex and...
Dr
Jinyuan Wu
(Fermilab)
23/09/2014, 17:09
Signals with various timing relations can be generated inside FPGA conveniently with internal phase lock loop
(PLL) blocks. When multiple PLL blocks are cascaded together. In this paper, clocks
generated by cascaded PLL with slightly difference in frequencies are studied. They are used to produce
pulse pairs with precise timing delay control at 0.98 ps/step. They are also used to...
Gary Drake
(Argonne National Laboratory (US))
23/09/2014, 17:11
We present results from recent radiation tolerance tests that we have performed on prototype boards and components for the front-end electronics intended for the upgrade of the hadronic calorimeter (TileCal) for the ATLAS experiment at the LHC. The tests include Total Ionizing Dose (TID) tolerance, Non-Ionizing Energy Loss (NIEL) tolerance, and Single Event Effects (SEE) tolerance. We...
Jose Carlos Rasteiro Da Silva
(LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
23/09/2014, 17:13
The calorimeter trigger of the CMS experiment at the LHC uses Synchronization and Link Boards (SLB) to perform the synchronization of trigger primitives (TP) from the electromagnetic and hadronic calorimeters and transmit these TPs to the Regional Calorimeter Trigger (RCT). During the first long shutdown, the SLBs will be replaced by optical SLBs (oSLBs) and the receiver mezzanines (RM) in the...
Andrea Abba
(Università degli Studi e INFN Milano (IT))
23/09/2014, 17:14
Our research aims to develop a specialized track processor capable of precisely reconstructing events with hundreds of charged-particle tracks in pixel and silicon strip detectors at 40 MHz. For this purpose we design and test a massively parallel, neurobiology-inspired, pattern-recognition algorithm. Here we present the R&D for a first prototype of silicon tracker with trigger capabilities...
Dr
Babak Rahbaran
(Austrian Academy of Sciences (AT))
23/09/2014, 17:15
The Global Trigger (GT) is the final step of the CMS Level-1 Trigger and implements the “menu'' of triggers, which is a set of selection requirements applied to the final list of objects (such as muons, electrons or jets) to trigger the readout of the detector and serve as basis for further calculations by the High Level Trigger. Operational experience in developing trigger menus from the...
Dr
Jaroslaw Szewinski
(NCBJ Swierk)
23/09/2014, 17:16
The MTCA electronics standard, except the high performance fast serial links on the backplane, provides also extensive management of the devices in crate.
Each AMC board must have MMC implemented to get power in the MTCA crate, which in many cases is barrier for new users to switch to MTCA.
This presentation/poster will show details and aspects of the MMC implementation developed at DESY for...
Nate Rider
(Cornell University)
23/09/2014, 17:17
We present the design of a 5 channel 800 MSPS uTCA based digitizer that will be deployed in the the Muon g-2 Experiment at Fermilab. The digitizer features 12-bit 800 MSPS digitizers with dedicated 1Gbit memory buffers. Multiple Xilinx Kintex-7 FPGAs provide the control and coordination within the digitizer. Provisions for a modular front end allow for application specific analog signal...
Thierry Romanteau
(Ecole Polytechnique (FR))
23/09/2014, 17:18
The CMS experiment implements a two-level online selection system. The first level is based on coarse information coming from the calorimeters and the muon detectors while the High Level Trigger combines fine-grain information from all sub-detectors. During Run II, the goal is to maintain the current thresholds (e.g., for electrons and photons) and improve the performance for the selection of...
Gilbert Herrera
(Sandia National Laboratories)
24/09/2014, 09:00
Sandia’s MESA complex includes both silicon and compound semiconductor fabs and over 100 laboratories, staffed by 500 scientists, engineers, and technologists. In addition to radiation-hardened silicon and III-V process technologies, Sandia conducts R&D through product delivery in a wide array of nanoscale and microscale technologies, including many relevant to the particle physics community....
Dimitrios Marios Kolotouros
(University of Ioannina (GR))
24/09/2014, 09:50
A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being proposed to replace the existing off-detector TTC system used by the LHC experiments. High split ratio, dynamic software partitioning, low and deterministic latency, as well as low jitter are required. Exploiting the latest available technologies allows...
Paolo Carniti
(Universita & INFN, Milano-Bicocca (IT))
24/09/2014, 10:15
The CLARO-CMOS is a prototype ASIC for fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of about 1 mW per channel. The chip was designed in 0.35 micron CMOS technology, and was tested for radiation tolerance with neutrons up to 10$^{14}$ 1 MeV neq/cm$^2$ and protons and X-rays up to 8 Mrad. Its capability to readout single...
Mark Pesaresi
(Imperial College Sci., Tech. & Med. (GB))
24/09/2014, 10:15
The FC7 is a flexible, μTCA compatible Advanced Mezzanine Card (AMC) for generic data acquisition/control applications. Built around the Xilinx Kintex 7 FPGA, the FC7 provides developers with a platform which has access to a large array of configurable I/O, primarily delivered from onboard FPGA Mezzanine Card (FMC) headers. Targeting users of high speed optical links in high energy physics...
Rui Gao
(University of Oxford (GB))
24/09/2014, 11:10
The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. It combines Time-Of-Flight and Cherenkov techniques to achieve particle separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons. Existing electronics has already demonstrated a 26ps intrinsic timing resolution, however the channel density needs improvements...
Ludovic Raux
(OMEGA Ecole Polytechnique -CNT)
24/09/2014, 11:10
The SPIROC and TRIROC chips are complete dedicated very front-end electronics for the readout of SiPM. Designed with AMS 0.35 µm SiGe technology, they enable to digitize and process signal over such a large dynamic range ADC.
SPIROC has been extensively used for calorimeters by different groups for ILC (International Linear Collider) HCAL and ECAL prototypes.
With its 64-channel readout,...
Eduardo Picatoste Olloqui
(University of Barcelona (ES))
24/09/2014, 11:35
An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and includes...
Antonio Orzelli
(INFN Genova)
24/09/2014, 11:35
The KM3NeT neutrino telescope will be composed of many optical modules, each of them containing 31 (3") photomultipliers, connected to a Central Logic Board. The Central Logic Board integrates Time to Digital Converters that measure Time Over Threshold of the photomultipliers signals while White Rabbit is used for the optical modules time synchronization. Auxiliary boards have also been...
Jakub Moron
(AGH University of Science and Technology (PL))
24/09/2014, 14:00
The design and preliminary measurement results of a multichannel, variable gain front-end electronics for LumiCal detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier and CR-RC shaper with pole-zero cancellation circuit. Measurement results confirm full...
Mr
Manfred Kirchgessner
(University Heidelberg)
24/09/2014, 14:00
The readout chain of the DSSC 1Megapixel detector currently built at DESY, Hamburg for the European X-Ray Free Electron Laser XFEL.EU is described.
The system operates in a pulsed mode comparable to the new ILC. 800 images of 1Megapixels (9 bit per pixel) are produced at a rate of 10 Hz leading to a total throughput requirement of 144 GBit/s.
In order to deal with the high data rates, the...
Prof.
Yun Chiu
(The University of Texas at Dallas)
24/09/2014, 14:25
We present the design of a 12-bit, 160-MSPS two-step SAR ADC in 40-nm CMOS with calibration and radiation test results. The ADC measured 67.5-dB SNDR and ≥85-dB SFDR that displayed minimal degradation after being exposed to a total ionizing dose of up to 1 Mrad. The power consumption is 4.5 and 6.1 mW at 80 and 160 MSPS, respectively. The small die size also opens up good potential for single...
Tom Williams
(University of Bristol (GB))
24/09/2014, 14:25
The xTCA standards define pathways for control communication, but no specific hardware control protocol is defined. The IPbus suite of software and firmware implements a reliable high-performance control link for particle physics electronics, and has succesfully replaced VME control in several large projects. In this talk, we outline the IPbus system architecture, and describe recent...
Gianluigi De Geronimo
(Brookhaven National Laboratory (US))
24/09/2014, 14:50
We present VMM2, an ASIC for charge-interpolating trackers designed for use with Micromegas and sTGC in the ATLAS Muon upgrade. It integrates 64 channels, each providing charge amplification, discrimination, neighbor logic, amplitude and timing measurements, analog-to-digital conversions, and either direct or multiplexed readout. The front-end amplifier can operate with a wide range of input...
Mr
Jeffrey Prinzie
(KU Leuven)
24/09/2014, 15:15
A radiation hardened Time-to-Digital Converter (TDC) has been designed with < 10 ps single-shot resolution using resistive interpolation. The TDC uses a DLL based control loop to calibrate gate delays to a reference clock. The control loop uses a novel low bandwidth Bang-Bang phase detector in combination with a high bandwidth dead-zone PFD for fast recovery after single-event strikes. The...
Yasuyuki Okumura
(University of Chicago (US))
24/09/2014, 15:15
The first stage of the ATLAS Fast TracKer (FTK) is an ATCA-based input interface system, where hits from the entire silicon tracker must be clustered and organized into overlapping eta-phi trigger towers before being sent to the tracking processors. First, FTK Input Mezzanine cards receive hit data and perform clustering to reduce data volume. Then, the ATCA-based Data Formatter system will...
Gianluca Traversi
(Universita e INFN (IT))
24/09/2014, 15:40
This work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65nm CMOS technology. Together with a conventional structure which exploits bipolar...
Nicola De Simone
(Universita e INFN Roma Tor Vergata (IT))
24/09/2014, 15:40
The setup of the experiment NA62, studying ultra-rare decays of
charged kaons at the CERN SPS, is going to be completed for the first
physics data taking in the autumn of 2014. We present the final design,
implementation and the first on-field performance tests of the Level-0
trigger system of the Liquid Krypton calorimeter, photon veto in the
1-10 mrad region. The system is composed of...
Ivo Polak
(Acad. of Sciences of the Czech Rep. (CZ))
24/09/2014, 16:45
The gain of SiPMs depends both on bias voltage and on temperature. We can compensate the temperature variation by regulating the bias voltage. We have developed and built an adaptive bias voltage regulator and performed tests in a climate chamber at CERN. Over a temperature range 1 – 40 degrees C we have tested the performance of the bias voltage regulator with five SiPMs / MPPCs from three...
Andrea Biagioni
(INFN Rome Section)
24/09/2014, 16:46
In this paper we describe the latest generation of APEnet+ network interface card.
This new APEnet+ generation delivers a point-to-point, low-latency, 3D-torus NIC integrated in a PCIe Gen3 board based on a state-of-the-art, 28nm Altera Stratix V FPGA.
The NIC features a network architecture designed following the Remote DMA paradigm and tailored to tightly bind the computing power of modern...
Eduard Atkin
(NRNU MEPHI)
24/09/2014, 16:47
A new approach to design of amplification blocks (such as preamps, shapers) is described. The generalized block diagram and analytic expressions for its transfer function are presented. The particular cases of this structure are classical schemes, using either the voltage or current feedback, but not limited by them.
The discussed formulas can be useful for the design of a whole range of...
Philipp Schwegler
(Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
24/09/2014, 16:49
We report on the high-rate optimisation of a new Amplifier/Shaper/Discriminator (ASD) chip for the ATLAS Monitored Drift Tube (MDT) chambers, which have to sustain an unprecedented radiation background during LHC operation. The design of a new ASD chip is inevitable to provide enough chips for future upgrades of the MDT chamber front-end electronics and desirable to optimise the shaping...
Dr
Christophe FLOUZAT
(CEA Centre de Saclay)
24/09/2014, 16:50
In the framework of the ALICE experiment upgrade at HL-LHC, a new tracking detector, the Muon Forward Tracker, is foreseen. To fulfill detector requirements, CMOS Monolithic Active Pixel Sensor (MAPS) technology was chosen thanks to interesting performances and properties in terms of readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This...
Matteo Di Cosmo
(Ministere des affaires etrangeres et europeennes (FR))
24/09/2014, 16:53
The MicroTCA and AdvancedTCA industry standards are candidate modular electronics platforms for the upgrade of the current generation of high energy physics experiments at CERN. The PH-ESE group at CERN launched an xTCA evaluation project with the aim of performing technical evaluations and providing support for commercially available components. Over the past years, different equipment from...
Dr
Dong Wang
(Central China Normal University)
24/09/2014, 16:54
The ALICE PHOS collaboration is carrying out a major upgrade of its readout electronics for the RUN 2 of LHC (2015-2017). The upgrade mainly includes three aspects: 1) The increase of the event readout rate; 2) The improvement of the communication stability of the interface between Front-end electronic boards and readout concentrators; 3)The compatibility to the upgraded ALICE Trigger system...
Mr
Robert Schnell
(Justus-Liebig-Universitaet Giessen (DE))
24/09/2014, 16:55
The PANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons on stationary targets. The Micro-Vertex-Detector (MVD) as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors.
Developments for the readout of the strip detectors,...
Developments for the readout of the strip detectors,...
Luigi Gaioni
(Università di Bergamo)
24/09/2014, 16:57
Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed,...
Joonas Petteri Talvitie
(Lappeenranta Univ. of Technology (FI))
24/09/2014, 16:59
Developed for use with triple GEM detectors; the GEM Electronics Board (GEB) forms a crucial part of the electronics readout system being developed as part of the CMS muon upgrade. The objective of the GEB is three-fold; to provide stable powering and ground for VFAT3 front ends, to enable high speed communication between 24 VFAT3 front ends and an Optohybrid, and to shield the GEM detector...
21.
MicroTCA.4 for Industry and Research – Experiences with the Introduction of a New Crate Standard
Katharina Fein
(DESY)
24/09/2014, 17:01
MicroTCA.4 is a novel electronic standard derived from the Telecommunication Computing Architecture (TCA) and rapidly evolved to become a viable standard for demanding applications in large-scale research facilities of the high-energy physics and photon science community. DESY has taken on a coordinating role in the further development of MicroTCA.4 components as well as the further...
Pedro Vicente Leitao
(CERN)
24/09/2014, 17:02
This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements bidirectional 4.8 Gb/s links between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional tests of the GBTX and to evaluate its performance. Total Ionizing Dose and Single-Event...
Jose Luis Sirvent Blasco
(University of Barcelona (ES))
24/09/2014, 17:03
A secondary particle shower acquisition system is under design for the new CERN wire scanner-based beam profile monitors. In these systems a thin wire passes through a circulating beam and the resulting secondary particles are detected to reconstruct the beam profile. It is proposed that the new acquisition system be based on a polycrystalline diamond detector (pCVD). The accompanying...
Erdem Motuk
(University College London)
24/09/2014, 17:04
The firmware structure and system integration of the final Clock and Control (CC) hardware for the EuXFEL 2D mega-pixel detectors are presented. The hardware was developed as a combination of an AMC board and a custom RTM that would work in a MTCA.4 crate. The firmware consists of a number of modules interconnected around a bus/register system that communicates to the control system over PCIe....
Prof.
Jinghong Chen
(University of Houston, Texas)
24/09/2014, 17:05
We present a new charge-compensation (CC) scheme to mitigate single-event-transient effect in designing a phase-locked loop. The CC method significantly reduces SET-induced voltage perturbation at the oscillator control node as well as a faster recovery. It is triggered only when SET strikes occurs and thus does not affect normal PLL dynamics. The PLL achieves a 12.5MHz to 500MHz tuning range...
Robert Stringer
(University of Kansas (US))
24/09/2014, 17:06
The Phase I Upgrade to the CMS Pixel Detector at the LHC features a new 400 Mb/s digital readout system. This new system utilizes upgraded custom ASICs, PSI46dig Read Out Chips (ROC) and Token Bit Manager (TBM08/09) for data packaging, new optical links, and changes to the Front End Drivers (FEDs). We will be presenting the new architecture of the full readout chain, the new schema for data...
Lluís Freixas Coromina
(C)
24/09/2014, 17:07
An application specific integrated circuit (ASIC) has been developed for level 1 trigger decisions in Cherenkov Telescope cameras. The ASIC comprises 7 input differential analogue channels and 2 output digital differential channels. Analogue inputs are provided by the previous trigger stage implemented in the so-called L0 ASIC. The L1 ASIC computes the analogue sum of three configurable sets...
Agnieszka Anna Zagozdzinska
(Warsaw University of Technology (PL))
24/09/2014, 17:08
The Beam Radiation Instrumentation and Luminosity Project of the CMS experiment, consists of several beam monitoring systems. One system, the upgraded Fast Beams Condition Monitor, is based on 24 single crystal CVD diamonds with a double-pad sensor metallization and a custom designed readout. Signals for real time monitoring are transmitted to the counting room, where they are received and...
Stephen Goadhouse
(University of Virginia (US))
24/09/2014, 17:10
In the CMS Hadron Calorimeter, the Clock Control Module distributes the system clock to the readout modules and supports control and monitoring of the front-end electronics. This year an upgrade prototype, called ngCCM, has been built and used for a beam-test of the upgraded Forward HCAL. The ngCCM uses a 4.8 Gbps GBT-like optical link to the counting room along with a redundant mechanism in...
Prof.
Jinghong Chen
(University Of Houston, Texas)
24/09/2014, 17:12
This paper presents a LC-VCO PLL designed in 0.13μm CMOS technology for multi-data rate serial link applications. The PLL covers a 5.6GHz to 13.4GHz tuning range by using two LC-VCO cores while remaining locked from -40°C to 85°C. At 25°C, the PLL has a RMS random jitter (RJrms) of 0.37pS at 11.44GHz. The integrated jitter is less than 0.7pS. The PLL consumes 50.88mW of power from a 1.2V...
Mr
Juan Carlos Allica
(CERN)
24/09/2014, 17:14
At the CERN PS complex, precise fast intensity measurements are very important in order to optimize the transfer efficiencies between the different accelerators. Over the last two years a complete renovation has been ongoing, where the old electronics, based on analogue integrators, have been replaced by a fully digital system enclosed in a single VME based card.This new system called TRIC...
Tiankuan Liu
(Southern Methodist University)
24/09/2014, 17:15
We present a remote FPGA-configuration method based on JTAG extension over optical fibers. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or software development. The method combines the advantages of the slow remote JTAG configuration and the fast local flash memory configuration. We have verified that we can...
Tiankuan Liu
(Southern Methodist University)
24/09/2014, 17:16
A prototype Liquid-argon Trigger Digitizer Board (LTDB), called LTDB Demonstrator, has been proposed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog/Digital converters and four FPGAs with embedded multi-gigabit-transceivers on each Demonstrator need high quality clocks. A clock distribution system based on commercial...
Evgeny Malankin
(NRNU MEPhI)
24/09/2014, 17:18
A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power budget of 10mW per channel, area efficient 1.2 mW at 50 Msps 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow),...
Christian Torgersen
(University of Bergen (NO))
24/09/2014, 17:19
A new readout control unit for the ALICE TPC in Run-2 - the RCU2 - has been designed in order to increase data throughput and radiation tolerance. Since the TTCrx ASIC project is disbanded, new ways to recover clock and data was implemented and tested. Two methods have been applied, one using the internal fabric resources of the SmartFusion2 FPGA and the other using a commercial component, the...
Per Olov Joakim Gradin
(Uppsala University (SE))
24/09/2014, 17:20
The LHC plans to increase the design instantaneous luminosity by a factor of five.
The ATLAS experiment will upgrade its trigger and DAQ systems to preserve the acceptance
for electro-weak processes without increasing thresholds on the transverse momenta of physics objects.
The new scheme includes additional hardware to decouple a short latency system
from a longer latency one using the...
Fatah Rarbi
(IN2P3 / LPSC Grenoble)
24/09/2014, 17:22
The PEALL chip is a Power Efficient And Low Latency successive approximation register (SAR) ADC candidate designed for the upgrade of the ATLAS experiment at the CERN LHC. The full functionality of the converter is especially achieved by an embedded high-speed clock frequency conversion generated by the ADC itself. The design and test results of the PEALL chip implemented in a commercial...
Manoel Barros Marin
(CERN)
24/09/2014, 17:23
Initiated in 2009 to emulate the GBTx serial link and test the first GBTx prototypes, the GBT-FPGA project is now a full library, targeting FPGAs from ALTERA and XILINX, allowing the implementation of one or several GBT links of 2 different types: “Standard” or “Latency-Optimized”. The first major version of this IP Core was released in April 2014. This paper presents the various flavours of...
Marcos Vinicius Silva Oliveira
(Juiz de Fora Federal University (BR))
24/09/2014, 17:24
For run 2 of the LHC, the ATLAS Level-1 trigger system will include
topological information on trigger objects in order to cope with the
increased trigger rates. The existing Muon-to-Central-Trigger-Processor interface (MUCTPI) has been modified in order to provide
coarse-grained topological information on muon candidates. A MUCTPI-to-Level-1-Topological-Processor interface (MuCTPiToTopo)...
Daniel Magalotti
(Universita e INFN (IT))
24/09/2014, 17:25
The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions.
To extract in the required latency the track information a dedicated hardware has to be used. We propose a...
Mieczyslaw Maria Dabrowski
(Warsaw University of Technology (PL))
24/09/2014, 17:26
Intended for implementation within the VFAT3 ASIC; the VFAT3-Comm-Port offers a single port for clock, synchronization, fast and slow control commands as well as data and slow control readout. The paper initially describes the core design which could be offered for use as an IP block in other projects. It also discusses an encoding technique which provides unique comma characters and increases...
Tetsuichi Kishishita
(University of Bonn)
24/09/2014, 17:28
We present the recent development of the depleted Monolithic Active Pixel Sensors, implemented with an L-Foundary 150 nm process. Unlike in the case of standard MAPS technologies, this process provides a high-resistive substrate that enables large signal and fast charge collection by drift in a 50 um – 100 um thick depleted layer, and the use of PMOS and NMOS transistors in the pixel cell...
Dr
Jun Hu
(Institute of High Energy Physics, Chinese Academy of Sciences(IHEP,CAS))
24/09/2014, 17:30
The underground dark matter experiment in IHEP is direct detection of dark matter that using CsI(Na) as detector material, and rare nuclear recoil events of dark matter particles scattering on target material will be detected by photo-multiplier tubes (PMTs). This paper describes the electronics system structure we chosen for this detector; emphatically focus on the design of main modules that...
55.
Design and Testing of Combined GEM+CSC Trigger Algorithm Firmware for the CMS Muon Endcap System
Aysen Tatarinov
(Texas A & M University (US))
24/09/2014, 17:31
With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require more complex trigger algorithms to handle the increased data rate while maintaining high data collection efficiency. Higher performance trigger electronics have already been deployed in the front-end, and advanced trigger logic is under development to take advantage of the capabilities in the...
Vagelis Gkougkousis
(Universite de Paris-Sud 11 (FR))
24/09/2014, 17:32
Innovative edgeless planar pixel sensors for the High Luminosity LHC upgrade are under production. Through 3D TCAD simulation of the production process and electric field at the inside of the detector, combined with SiMS measurements, a calibration and complete insight of the new structures is achieved. Comparison between simulated data and experimental measurements allow a calibration of the...
Mr
Sergey Katunin
(PNPI St Petersberg)
24/09/2014, 17:33
Sound velocity measurements can simultaneously determine gas composition and flow. We have developed ultrasonic analyzers with custom microcontroller-based electronics, currently used in the ATLAS detector control system, with numerous applications.
Three instruments monitor C3F8 and CO2 coolant leak rates into the nitrogen envelopes of the ATLAS silicon microstrip and pixel detectors. Two...
Tiehui Ted Liu
(Fermi National Accelerator Lab. (US))
24/09/2014, 17:34
The challenge of the Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project is to increase pattern density through aggressive Vertical Integration. Our first step is to implement in conventional VLSI building blocks that can be used in 3D stacking. We are reporting on the first successful implementation of a conventional 2D demonstrator of the VIPRAM chip...
Jasmin Fragnaud
(Centre National de la Recherche Scientifique (FR))
24/09/2014, 17:35
The trigger readout electronics of the ATLAS LAr Calorimeters will be improved for the Phase-I luminosity upgrade of the LHC to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being set up which...
Alessandro Lonardo
(Universita e INFN, Roma I (IT))
24/09/2014, 17:55
NaNet is a FPGA-BASED PCIe Network Interface Card with GPUDirect capability featuring a configurable set of channels: standard 1/10GbE and custom 34Gbps APElink and 2.5Gbps optical with deterministic latency KM3link.
GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing.
We will...
John Porter
(Sandia National Laboratories)
25/09/2014, 09:00
A hybrid pixel detector with 25µm pitch has been developed to record multiple x-ray images with integration times as short as 1ns to measure the implosion dynamics of inertial confinement fusion experiments. The 1024x448 pixel detector is fabricated with Sandia’s 0.35µm technology and consists of a silicon diode array directly bonded to a CMOS ASIC. The ASIC incorporates a global shutter with...
Mr
Vladimir Gromov
(Nikhef)
25/09/2014, 10:14
We report on a prototype of a 5.12 Gbps Data Serializer and Wireline Transmitter circuit in 130 nm CMOS technology. A shift-register-free topology has been used in the serializer block. A 16-to-1 multiplexer selects one bit of data at a time from either a posedge triggered section or a negedge triggered section of a 16-bit input register clocked at 320 MHz. The serializer consumes only 15 mW...
Jamieson Olsen
(Fermilab)
25/09/2014, 10:15
The Pulsar II is an FPGA-based full mesh ATCA processor board capable of creating a scalable architecture abundant in flexible, high bandwidth interconnections. The resulting full mesh interconnection among FPGAs is a natural fit for spatial and time multiplexed data processing. The design has been motivated by silicon-based tracking trigger needs for the LHC experiments. Near term...
Ms
Xiaoting Li
(Central China Normal University, Southern Methodist University)
25/09/2014, 11:10
We present the designs and testing results of a single-channel and a two-channel VCSEL driver and a four-channel array VCSEL driver ASICs for the LHC detector upgrade. All ASICs are fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 are designed to drive differentially VCSEL TOSAs, whereas LOCld4 is designed to drive a VCSEL array die. LOCld1/LOCld2 and...
Heiko Engel
(Johann-Wolfgang-Goethe Univ. (DE))
25/09/2014, 11:10
The ALICE and ATLAS DAQ systems read out detector data via point-to-point serial links into custom hardware modules, the ALICE RORC and ATLAS ROBIN. To meet the increase in operational requirements both experiments are replacing their respective modules with a new common module, the C-RORC. This card, developed by ALICE, implements a PCIe Gen 2 x8 interface and supports twelve optical links...
Marc Winter
(Institut Pluridisciplinaire Hubert Curien (FR))
25/09/2014, 14:00
CMOS Pixel Sensors (CPS) exploit the features of CMOS industry to achieve highly granular and thin sensors with integrated front-end electronics. The concept is being developed since the late nineties and benefits from the steady evolution of industrial ASIC and imager industry.
The talk will overview intrinsic features of CPS, highlighting the technology potential. It will next discuss pros...
Ryan Christopher Edgar
(University of Michigan (US))
25/09/2014, 14:50
The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the ATLAS forward region. The large LV power demands of the NSW necessitate a point-of-load architecture with on-detector power conversion. The radiation load and magnetic field of this environment, while significant, are nevertheless still in the range where commercial-off-the-shelf power devices...
Prof.
Kock Kiam Gan
(Ohio State University (US))
25/09/2014, 15:15
New fiber optic transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed on the ATLAS pixel detector and for the new pixel layer. Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver/driver ASICs. The new opto-board design benefits from the first generation production and operational...
Dr
Katja Klein
(RWTH Aachen)
25/09/2014, 15:15
The CMS Phase-1 Pixel detector, to be installed in the year-end technical stop 2016/17, will feature a power system based on DC-DC conversion. The power system, including the final DC-DC converters based on the FEAST2 ASIC by CERN, DC-DC main boards, power distribution PCBs, power supplies and thermal management, will be described, and the performance of the components will be discussed. The...
Dr
Enrico Giulio Villani
(STFC RAL)
25/09/2014, 15:40
The increased luminosity of the HL-LHC will require more channels in the upgraded ATLAS Tracker, as a result of the finer detector segmentation.Thus, a more efficient power distribution and HV biasing of the sensors are among the many technological challenges facing the ATLAS Tracker Upgrade. A number of approaches, including the sharing of the same HV line among several sensors and suitable...
Tiankuan Liu
(Southern Methodist University)
25/09/2014, 15:40
A compact radiation-tolerant Array Optical transmitter module (ATx) integrating micro optics, a VCSEL array and a custom driver is demonstrated. ATx uses an edge warp substrate for the electrical interface and micro-lens array for the optical interface. A simple, high-accuracy and reliable active alignment method for micro-lens assembly is introduced. The coupling insertion loss is less than...
Kostas Kloukinas
(CERN)
25/09/2014, 16:30
Sandro Bonacini
(CERN)
25/09/2014, 16:45
Federico Faccio
(CERN)
25/09/2014, 17:00
Jorgen Christiansen
(CERN)
25/09/2014, 17:15
Emily Van der Heijden
(STFC)
25/09/2014, 17:30
Dr
Paul O'Connor
(Department of Physics)
26/09/2014, 09:45
The Large Synoptic Survey Telescope (LSST) is the flagship US ground-based optical astronomy facility for the next decade. At the heart of its 3Gpixel camera are the 21 focal plane modules, each of which is a fully autonomous and serviceable unit comprised of 9 CCDs and 144 channels of low-noise processing electronics. To minimize noise, power, and beam obscuration the electronics is...
Daniel Muenstermann
(Universite de Geneve (CH))
26/09/2014, 10:10
We explore the concept of using deep-submicron HV-CMOS and/or imaging processes to produce a drop-in replacement for radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a readout chip. This approach yields most advantages of MAPS, without the complication of full integration on a single chip.
After outlining the...
Mohsine Menouni
(Centre National de la Recherche Scientifique (FR))
26/09/2014, 11:05
The radiation tolerance of the 65 nm bulk CMOS devices is investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 10 MGy and the implications on the DC performance of n and p channels transistors are presented.
For a dose level of 10 MGy, transconductance loss is near 100% for the narrow channel pmos device making the device completely off.
Annealing at 100°C helps devices to...
Sarah Seif El Nasr
(CERN, University of Bristol (GB))
26/09/2014, 11:30
We report on our recent investigation into the potential for using silicon-based Mach-Zehnder modulators in the harshest radiation environments of the High-Luminosity LHC. The effect of ionizing and non-ionizing radiation on the performance of the devices have been investigated using the 20 MeV neutron beam line at the Cyclotron Resource Centre in Louvain-La-Neuve and the X-ray irradiation...
Jean-Pierre Cachemiche
(Centre National de la Recherche Scientifique (FR))
26/09/2014, 12:20
Other
HUGO DANIEL HERNANDEZ HERRERA
(Polytechnic School of the University of São Paulo)
ASICs
Poster
We will present the technical details of a new 130 nm CMOS ASIC, aimed to replace the present front-end electronics of two detectors (TPC and MCH) of the ALICE-LHC experiment. The SAMPA ASIC is an evolution of the presently used TPC front-end electronics in several ways. The SAMPA ASIC will provide of 32 channels either negative or positive polarity operation, 2 peaking time and 3 sensitivity...
