As part of a new wire scanner design being pursued by CERN, it is proposed to upgrade the secondary shower acquisition system.
The current system consists of a scintillator, optical filters and photo multiplier tube (PMT) with nearby pre-amplifier. The analogue signal is directly sent through long coaxial cables (up to 250m) to the surface, where the digitization is performed. The dynamic range is covered by selecting a combination of optical filter values and PMT gains. This requires knowing beforehand the beam characteristics expected when making a measurement. Effects such as PMT saturation can therefore lead to incorrect measurements, and the limited dynamic range in any configuration does not allow a correct measurement of the tails in a beam profile.
The new electronic design aims to cover the whole dynamic range expected from all CERN’s wire scanners with a single configuration, and be capable of bunch by bunch measurements with an integration time of 25ns. To be fully independent of the scanner location and beam parameters, a dynamic range of 1e6 has been calculated to be needed. The electronics must also resist a total ionisation dose of up to 1kGy in 10 years.
A front-end and back-end architecture is the baseline solution, with the signal digitization performed in the tunnel and the digital data sent though optical fibres to the back-end electronics in the service buildings.
Polycrystalline chemical vapour deposition diamond (pCVD) detectors will be used as sensor, for its high radiation tolerance, linearity and fast response. For the pCVD signal readout it is foreseen to use radiation tolerant integrator ASICs. At this stage of the project, two options are currently being pursued: the QIE10, designed by FERMILAB for the CERN CMS collaboration and the ICECAL, designed by University of Barcelona for CERN LHCb collaboration. The QIE10 is a charge integrator with 17 bit (1e5) dynamic range followed by an encoder providing the charge information in 8 bits with automatic range selection. The ICECAL is a 4 channel very low noise charge integrator with a 12 bit (4e3) dynamic range that provides an analogue signal for subsequent digitization. In both cases full coverage of the expected signal dynamic range will be performed by splitting the pCVD signal and using two or three channels in parallel with different gain/attenuation factors.
For the digital data transmission and synchronization it is planned to use the GigaBit Transceiver (GBTx) and Versatile Link (VTRx) components being developed for the LHC experiments. These components offer a radiation hard, bidirectional optical link at 4.8 Gbps.
The contribution will show a first front-end prototype/demonstrator system based on a Flash-Based Igloo2 FPGA development kit with customized GBTx emulation firmware to drive the optical link.