Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Front End Electronics for SOI Monolithic Pixel Sensor

Sep 23, 2014, 11:35 AM
Amphi Cezanne (Centre des Congrès - Aix en Provence, France)

Amphi Cezanne

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100


Toshinobu Miyoshi (KEK)


SOI monolithic pixel sensor has been developed using 0.2 um SOI pixel process technology. Pixel diodes are formed on SOI substrate and then pixel front end electronics are formed in 40nm thin SOI layer. Tungsten vias are used to connect the diode and electronics. A simple source follower circuit, charge sensitive preamplifier, comparator, and counter are designed in a pixel area. The minimum pixel area is 8 um square with typical 3 transistor cell and a diode. In the presentation, performance test results, problems and solutions are described.


SOI monolithic pixel sensors have been developed since 2005 using 0.2 um SOI pixel process technology. Any bump bonding technique is not used, and thus this is truly monolithic pixel sensor. Diodes are formed on SOI substrate and front end electronics are formed on 40nm thin SOI layer. Diodes and electronics are connected each other in the process. Since the connection area in the sensor contact is less than 1 um, sensor capacitance is very small and the sensor gain is high. The minimum pixel area using typical 3 transistor cell and a diode is 8 um square. Counting type pixel sensor is under development and the pixel includes a preamplifier, a comparator, 14 bit counter, and a diode within 50 um square. The resistivity and silicon wafer type of SOI substrate can be chosen and high resistivity n-type and p-type sensors have been developed. Since the sensor is very close to the circuit, the performance of pixel front end is affected by the back gate effect, in which high voltages at the back side of SOI wafer changes properties of transistors in the SOI layer. There are also crosstalk between sensor and front end electronics. Since thickness of silicon oxide is much larger than that of gate oxide of transistors, the performance is also affected by high dose radiation. To solve the problems, some novel processes were invented, and double SOI wafer was also utilized. When using double SOI wafer, the top SOI layer is used for readout electronics and the middle SOI layer is used as a shield to the back gate effect and crosstalk. The potential of the middle SOI layer can be controlled and therefore radiation hardness can also be improved. In the conference, properties of noise and gain, observation of crosstalk and effects of applied new process and double SOI wafer will be presented.

Reference: Arai et al.,"Development of SOI pixel process technology", Nucl. Instr. and Meth. A Vol 636, Supple. 21 April 2011, Pages S31-S36.

Primary author


Mr Ikuo Kurachi (KEK) Kazuhiko Hara (University of Tsukuba (JP)) Mr Kazuya Tauchi (KEK) Miho Yamada (High Energy Accelerator Research Organization (JP)) Shingo Mitsui (High Energy Accelerator Research Organization (JP)) Shunsuke Honda (University of Tsukuba (JP)) Dr Toru Tsuboyama (KEK, High Energy Accelerator Research Organization) Yasuo Arai (High Energy Accelerator Research Organization (JP)) Yoichi Ikegami (High Energy Accelerator Research Organization (JP)) Mr Yowichi Fujita (KEK) Yukiko Ikemoto (KEK)

Presentation materials