Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

DDL, the ALICE Data Transmission Protocol and its Evolution from 2 to 6 Gb/s.

Sep 23, 2014, 5:12 PM
1m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster Systems First Poster Session

Speaker

Filippo Costa (CERN)

Description

ALICE (A Large Ion Collider Experiment) is the detector system at the LHC (Large Hadron Collider) that studies the quark-gluon plasma. The information sent by the sub-detectors composing ALICE are read out by DATE (Data Acquisition and Test Environment), the ALICE data acquisition software, using hundreds of multi-mode optical links called DDLs (Detector Data Links). To cope with the higher luminosity of the LHC, the bandwidth of the DDL links will be upgraded in 2015. This paper will describe the evolution of the DDL protocol from 2 to 6 Gbit/s.

Summary

ALICE (A Large Ion Collider Experiment) is the detector system at the LHC (Large Hadron Collider) that studies the behavior of strongly interacting matter and the quark-gluon plasma. The information sent by the sub-detectors composing ALICE are read out by DATE (Data Acquisition and Test Environment), the ALICE data acquisition software, using several optical links. The data transmission protocol used by ALICE is called DDL (Detector Data Link). DDL is a bi-directional protocol that allows to read out data coming from the FEE (Front End Electronics) and to send slow control commands to the detectors. ALICE will face a partial upgrade in 2015, TPC and TRD will increase the acquisition rate to cope with the higher luminosity of the LHC. For this reason a faster version of the DDL has been developed, called DDL2. Currently all the detectors that send data to the ALICE DAQ system have installed on their FEE a daughter card called SIU (Source Interface Unit). The SIU sends data through optical fiber using the DDL protocol. The hardware of this card limits the max data throughput achievable by 2.125 Gb/s. The main difference between the DDL and DDL2 is the hardware implementation. The DDL2 doesn’t require a daughter card, but it distributed as VHDL code to be instantiated directly in the FPGA of the detector electronics. Replacing a daughter card with an IP core allows to have higher data throughput. Indeed the speed of the link is limited by the FPGA installed on the FEE and from the type of fiber used to send data. Instantiating the DDL core directly in the FPGA ease the upgrade of the protocol if new features are developed. To upgrade the SIU is required a direct access to the board, while the detector electronics firmware can be upgraded remotely.

Primary authors

Co-authors

Adriana Telesca (CERN) Alexandru Grigore (CERN) Mr Barthelemy Von Haller (CERN) Charles Delort (Ministere des affaires etrangeres et europeennes (FR)) Costin Ionita (CERN) Ervin Denes (Hungarian Academy of Sciences (HU)) Mr Franco Carena (CERN) Giuseppe Simonetti (Ludwig-Maximilians-Univ. Muenchen (DE)) Mr Pierre Vande Vyvre (CERN) Roberto Divia (CERN) Sylvain Chapeland (CERN) Tivadar Kiss (Hungarian Academy of Sciences (HU)) Ulrich Fuchs (CERN) Vasco Chibante Barroso (CERN) Wisla Carena (CERN)

Presentation materials