Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Design of Low-Power, Low-Voltage, Differential I/O Links for High Energy Physics Applications

Sep 23, 2014, 4:59 PM
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster ASICs First Poster Session


Gianluca Traversi (Universita e INFN (IT))


This work presents the design of a low-power, differential signaling, input/output data link in a 65 nm CMOS process for high-energy physics (HEP) experiments. The proposed driver is able to operate at 320 Mbps or 640 Mbps achieving a normalized power dissipation of 1.875 mW/Gbps. A pre-emphasis technique has been adopted to reduce the impedance mismatch between the driver output and the transmission line. This paper will discuss in detail the solutions implemented in the design and will describe the simulation results.


High performance electronic links able to transmit data in the gigabits-per-second range will be key components in future high-energy physics tracking systems. Low-Voltage Differential Signaling (LVDS) is a well-known and widely used technique to provide a low-power, high-speed I/O interface for point-to-point transmission. Although differential transmission doubles the number of the lines required to transmit information, it greatly improves the robustness of the link to power supply variation, and achieves low-power consumption together with low radiated electromagnetic interferences (EMI) with a good immunity to noise. A common LVDS transmitter can be modeled with a current generator with switched polarity. A 100 Ω differential load resistor at the receiver converts the current into a voltage signal with common-mode and differential-mode voltage that falls within the LVDS standard specifications. Since the proposed link will have to be used in a harsh radiation environment, the design is based on core transistor only, with thin gate oxide and a voltage supply of 1.2 V. This value is not compatible with the nominal common-mode voltage of the LVDS standard, which is 1.25 V. Moreover, the very low power dissipation constraint forced us to reduce the differential swing. The driver has been designed for the output stage of the Strip Sensor ASIC (SSA) and Macro Pixel ASIC (MPA) of the so-called Pixel-Strip (PS) module. The SSA chip sends data to the MPA chip through a wire bonding interconnection, while the MPA, after its sparsification procedure, sends the data to the concentrator chip through the Service Hybrid. In the worst-case scenario, this link will have to drive a ~10 cm long, 100 Ω differential line. The link operates at 320 Mbps or 640 Mbps with 600 mV common-mode voltage and 100 mV differential swing. The power dissipation is about 1.2 mW. This design will be integrated in a 65 nm CMOS technology test chip and submitted for fabrication in mid 2014. The full description of the driver and the receiver together with the simulation results will be provided in the conference paper.

Primary author

Gianluca Traversi (Universita e INFN (IT))


Francesco De Canio (Universita e INFN (IT)) Kostas Kloukinas (CERN) Lodovico Ratti (Universita e INFN (IT)) Luigi Gaioni (Universita e INFN (IT)) Massimo Manghisoni (Universita e INFN (IT)) Paulo Rodrigues Simoes Moreira (CERN) Sandro Bonacini (CERN) Valerio Re (Universita e INFN (IT))

Presentation materials