Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

The GBT-SCA, a Radiation Tolerant ASIC for Detector Control and Monitoring Applications in HEP Experiments

Sep 23, 2014, 5:00 PM
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster ASICs First Poster Session


Alessandro Caratelli (Sezione di Pisa (IT))


This work describes a radiation tolerant, monitoring and control ASIC for applications in HEP experiments. The GBT-SCA is part of the GBT optical link chip-set. Its purpose is to distribute control and monitoring signals to the on-detector front-end electronics for the upgrades of the LHC experiments. It is designed employing radiation hardening techniques and is fabricated in a commercial 130 nm CMOS technology. This contribution will present the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link.


The future upgrades of the LHC will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (GigaBit Transceiver optical link) architecture was developed providing the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA is part of the GBT chipset that facilitates the distribution of control and monitoring signals to the front-end electronics in HEP detectors. It connects to a dedicated electrical port on the GBTX ASIC through an 80Mbps double redundant bidirectional data-link.
In order to meet the requirements of different front-end ASIC of the different experiments, the SCA provides different fully user-configurable protocol ports that are able to perform simultaneous transfers: SPI, 16 independent I2C masters, JTAG master for boundary scan and firmware upload to FPGA devices and 32 general-purpose IOs/interrupt inputs. It also incorporates 31 analog inputs multiplexed in a 12 bit ADC (0.0V-1.0V) with offset calibration and gain correction techniques, four 8bits DACs and temperature control. To reduce power consumption, each channel interface can be keep in power-down mode when not in use. Radiation hardening techniques have been applied in order to ensure robustness against SEUs and TID effects. For this purpose have been developed scripts for speedup the state machine triplication and emulate single event upsets effects in simulation.
In this contribution we will present the overall architecture of the GBT-SCA ASIC describing in detail the design of the peripheral ports, the dual layer communication architecture, the system on chip interconnectivity and the techniques we have used to mitigate radiation effects.

Primary authors

Alessandro Caratelli (Sezione di Pisa (IT)) Kostas Kloukinas (CERN)


Presentation materials