Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

First Irradiation Tests Results of the ALICE TPC RCU2

Sep 23, 2014, 3:40 PM
25m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100

Speaker

Chengxin Zhao (University of Oslo (NO))

Description

This paper will present the first results from irradiation tests performed on the ALICE TPC Readout Control Unit 2 (RCU2). The RCU2 is developed in order to double the readout speed with respect to the present RCU1, which then will fulfill the requirements for LHC RUN2. While the present RCU1 is based on an SRAM based FPGA, which configuration memory has shown to be sensitive to single event upsets, the newly released Flash based Smartfusion2 FPGA from Microsemi has been chosen for the RCU2.

Summary

The time projection chamber (TPC) is one of the major sub-detectors of ALICE. It consist of 4356 Front-end cards (FECs) which are readout and controlled by 216 Readout Control Units (RCUs). Each RCU is connected to from 18 to 25 FECs with two branches of a multidrop Gunning Transistor Logic (GTL) Bus. In LHC RUN1, the readout speed is limited significantly by the parallel bus structure and additionally about 9% of the readout runs was aborted due to single event effects in the FPGA. In LHC RUN2, these limitations will become more critical since the interaction rate of Pb-Pb collisions will be increased from 3kHz to 10kHz. To overcome this the Readout Control Unit2 (RCU2) has been designed. For the RCU2, the GTL bus is split into four separate branches. Correspondingly, the bandwidth of the Detector Data Link (DDL) is increased from 1.6 Gbps to 3.125 Gbps (DDL2).

In RUN2, the expected radiation load on the TPC front-end electronics is increased from 0.8kHz/cm2 to3kHz/cm2. To minimize the risk of radiation induced failures, the Flash based Microsemi Smartfusion2 FPGA was therefore chosen due to its inherently Single Event Upset (SEU) tolerant configuration memory. This device is also among the first Flash based FPGAs that offers high speed serial interfaces which is necessary to support the high data rates.

Radiation induced effects can nevertheless be expected in clock distribution elements, memories and registers of the FPGA, in addition to external interfaces such as the DDL2 data link and the Trigger, Timing and Control (TTC) interface. Irradiation campaigns are therefore necessary to investigate the radiation tolerance of the RCU2. This paper will present the first results of these irradiation campaigns in addition to discuss relevant mitigation approaches necessary to reduce the impact of radiation induced failures during RUN2. The irradiation tests have mainly been performed at The Svedberg Laboraroty in Uppsala using their 180 MeV proton beam line.

Primary author

Chengxin Zhao (University of Oslo (NO))

Presentation materials