The first wafers of ABC130, a Front End ASIC for the ATLAS Silicon Strip, were received in November 2013.
A test plan was devised based upon the existing SCTDAQ software, as developed to evaluate earlier ATLAS binary strip readout chips, with SLAC’s HSIO board, running our own custom firmware, as a readout platform. In addition to the software and firmware modifications needed to communicate with the new chip, a suite of custom hardware was produced. The key component is a new driver board based upon a Xilinx Spartan-3A FPGA which interfaces the device under test with the HSIO. The driver provides level translation and buffering of fast signals between ABC130 and HSIO; it probes various monitor points by means of ADCs; it drives the chip’s static control nodes (addresses etc) by means of registers implemented within the Spartan chip. The hardware suite is completed by a single chip PCB, designed to hold one ABC130 chip with an optional mini strip sensor; a custom probe card for on-wafer testing; a simple variable frequency clock generator based around a commercial PLL chip to facilitate the exploration of margins. (The driver board may also drive hybrids with multiple ABC130 chips, but this is not documented here.)
The first wafer of chips was diced untested. First evaluation of chips bonded to single chip PCBs identified an error with the bidirectional SLVS transceiver blocks. Initially four devices were corrected by Focussed Ion Beam edit, these were successfully tested on single chip PCBs. Having gained confidence with the system, later FIB devices were tested using the custom probe card. The ABC130 design has been corrected and resubmitted, with wafers back from IBM this summer.
The poster will describe the custom driver board, probe card, firmware and software used to test ABC130. Subject to confirmation of delivery schedules, wafer probe results will also be shown.