22–26 Sept 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Depleted Monolithic Active Pixel Sensors with LF 150 nm CMOS

24 Sept 2014, 17:28
1m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster ASICs Second Poster Session

Speaker

Tetsuichi Kishishita (University of Bonn)

Description

We present the recent development of the depleted Monolithic Active Pixel Sensors, implemented with an L-Foundary 150 nm process. Unlike in the case of standard MAPS technologies, this process provides a high-resistive substrate that enables large signal and fast charge collection by drift in a 50 um – 100 um thick depleted layer, and the use of PMOS and NMOS transistors in the pixel cell without limitation. In order to evaluate the basic CMOS parameters and sensor characteristics, different pixel layouts and readout architectures were implemented. In this presentation, we will also report on the latest measurement results.

Summary

Since sensor and readout chip are both fabricated from a silicon substrate, the goal of detector physicists has always been to develop monolithic pixel detectors where these parts become one entity. So called Monolithic Active Pixel Sensors (MAPS) have been proposed and developed since the late 1990s using substrate wafers with an epitaxial layer underneath the electronics layer, in which charge can be collected at an n-type collection electrode, albeit by unordered and slow diffusion rather than by drift in a directed electric field.
On the other hand, conventional MAPS technologies have several intrinsic drawbacks, such as a small absorption probability in the thin epi-layer or non-usable of full CMOS logic in the active layers. To overcome such problems, we are currently developing depleted MAPS (DMAPS) with several commercial technologies. Unlike in the case of standard MAPS technologies, these DMAPS processes provide a high-resistive substrate that enables large signal and fast charge collection by drift in a 50 um – 100 um thick depleted layer, and the use of PMOS and NMOS transistors in the pixel cell without limitation.
In the latest development, we designed a DMAPS with an L-Foundary 150 nm process. In order to evaluate the basic CMOS parameters and sensor characteristics, different pixel layouts and readout architectures were implemented. In this presentation, we will also report on the latest measurement results and discuss the future prospect.

Primary author

Tetsuichi Kishishita (University of Bonn)

Co-authors

Dr Hans Krüger (University of Bonn) Norbert Wermes (Universitaet Bonn (DE)) Tomasz Hemperek (Universitaet Bonn (DE))

Presentation materials