Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Applications of Cascaded Phase Lock Loop (PLL) Blocks inside Field Programmable Gate Array (FPGA)

Sep 23, 2014, 5:09 PM
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster Logic First Poster Session


Dr Jinyuan Wu (Fermilab)


Signals with various timing relations can be generated inside FPGA conveniently with internal phase lock loop (PLL) blocks. When multiple PLL blocks are cascaded together. In this paper, clocks generated by cascaded PLL with slightly difference in frequencies are studied. They are used to produce pulse pairs with precise timing delay control at 0.98 ps/step. They are also used to generate calibration signals inside FPGA based TDC with evenly spread timing spectrum. The cascaded PLL can also be used for relative phase measurement of several input clocks. The firmware of the FPGA and the measurement results are presented.


To be added

Primary author

Dr Jinyuan Wu (Fermilab)

Presentation materials

There are no materials yet.