Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Proposed FPGA Based Tracking for a Level-1 Track Trigger at CMS for the HL-LHC

Sep 23, 2014, 4:58 PM
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster Trigger First Poster Session


Nicola Pozzobon (Universita e INFN (IT))


The High Luminosity LHC (HL-LHC) is expected to deliver a luminosity in excess of 5x10^34 cm^{-2}/s. The high eventrate places stringent requirements on the trigger. A key component of the CMS upgrade for the HL-LHC is a track trigger to identify tracks with transverse momentum above 2 GeV already at the first-level trigger within 5 us. This presentation will discuss a proposed track finding and fitting based on the "tracklet based approach" implemented on FPGAs. Tracklets are formed from pairs of hits in nearby layers in the detector and used in a road search.


Fast pattern recognition in Silicon trackers for triggering has often made use of Associative Memories for the pattern recognition step. We propose an alternative approach to solving the pattern recognition and track fitting problem for the upgraded CMS tracker for the HL-LHC operation. We make use of the trigger primitives, stubs, from the tracker. The stubs are formed from pairs of hits in sensors separated radially by a few millimeters. This allows us to place a pT cut on the stub and reject the vast majority of the hits from low pT tracks. In a typical bunch crossing at the HL-LHC we will have approximately 140 proton-proton interactions, producing about 10,000 stubs.

The proposed pattern recognition algorithm forms tracklets, seeds for the pattern recognition, by combining pairs of stubs in neighboring layers that are consistent with pT>2 GeV and the tracklet originating from the interaction region. These tracklets are used to define roads where stubs in other layers are added to form the complete track. A linearized chi^2 fit is used to obtain the final track parameters.

The implementation of this algorithm on an FPGA is done in sectors, where each sector is processed by one FPGA. In the first implementation of this algorithm we assume a time multiplexing of a factor of 4. In this presentation we will discuss the performance of the track finding algorithm and the resources used in the implementation.

Primary author

Nicola Pozzobon (Universita e INFN (IT))

Presentation materials