Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Building Blocks X-fab SOI 0.18µm

Sep 23, 2014, 5:01 PM
1m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster ASICs First Poster Session

Speaker

Mr Jean-Baptiste Cizel (LLR/Weeroc)

Description

Building blocks in the Silicon On Insulator 0.18 μm X-fab technology have been designed to study the future generation of SKIROC2 ASIC. These blocks are designed to characterize this technology as a possible candidate for the design of the final read-out ASIC of the Silicon Tungsten (SiW) Electromagnetic Calorimeter (ECAL) foreseen at the International Linear Collider. The performance of these building blocks will be compared to those of SKIROC2. The main parameters studied are noise, linearity, cross-talk, Power Supply Rejection Ratio, Single Event effects (SEU, SEL) and power consumption.

Summary

The SKIROC2 ASIC has been designed in the AMS SiGe 0.35 μm technology. It has been designed to read-out the Silicon Tungsten Electromagnetic Calorimeter foreseen at the International Linear Collider, which is the next generation of e+e- collider. The large digital part of this chip generates a non-negligible substrate noise that is difficult to completely shield and contributes significantly to the size and power dissipation of the chip. Therefore, a thinner technology on SOI with still performant analog transistors is a good alternative for this demanding calorimetric application.

To allow performance comparison, the general schematic of the analog part of SKIROC2 has been reproduced in the X-fab technology. The chip is made of a charge preamplifier followed by an adjustable gain and low gain slow shaper, a high gain slow shaper, a fast shaper, a discriminator, track and hold cells, a delay box, a Wilkinson ADC, a Threshold DAC and a bandgap. The detailed schematics have been changed to fit to the constraints of this technology and to fill the requirements of the experiment. The main requirements are:

• Trigger on a 2 fC positive input charge from 5x5 mm² PIN diodes ;

• Dynamic range from 0.1 to 2500 MIP;

• Internal dual gain 10-bit ADC ;

• Low power (25 μW/channel with a 0.5% power pulsing duty cycle)

The most challenging part was to conserve the analog performance of the AMS technology despite the lower power supply and the lack of bipolar transistors.

The preamplifier design has received careful attention in order to have a good compromise between noise, power consumption, power supply rejection and open loop gain. Open loop gain is an important issue as a single transistor has a relatively low gain (and so single stage amplifiers), making the 1% linearity difficult to achieve in the classic case of a common source PMOS preamplifier. Three different designs have been studied and will be characterized. These 3 designs are based on a NMOS common source, a PMOS common source and a 2-stage Miller OTA. The reduced power supply (1.8 V instead of 3.3V) precludes some usual architectures such as cascode. With the present design in X-fab, simulation results give a MIP to noise ratio of 13 at the fast shaper output and 1% linearity up to 2500 MIP at the low gain slow shaper output with the NMOS common source architecture. A 8-channel chip will be manufactured with different analog blocks in order to test channel-to-channel crosstalk and to compare performance of the various architectures. A vehicle test and isolated analog blocks will also be included in separate design and sent to the foundry.

To conclude, this work is mostly a comparison of these two technologies set in the context of a read out chip for the electromagnetic calorimeter’s detectors of the ILC.

Primary author

Mr Jean-Baptiste Cizel (LLR/Weeroc)

Presentation materials